cyclic.map.summary

基于fpga的屏幕测试程序

Flow Status : Successful - Sat Sep 29 16:37:17 2007
Quartus II Version : 5.0 Build 168 06/22/2005 SP 1 SJ Full Version
Revision Name : cyclic
Top-level Entity Name : cyclic
Family : Cyclone
Device : EP1C20F324C6
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 5,262
Total pins : 131
Total virtual pins : 0
Total memory bits : 113,664
Total PLLs : 0