hbars.tdf

基于fpga的屏幕测试程序

-- hbars.tdf
-- Based on Zhang Yuning's original work
-- Reworked by Chai Lin
-- 2006-08-27

include "fran_pg.inc";
include "lpm_rom.inc";
include "lpm_compare.inc";
include "lpm_add_sub.inc";
include "lpm_divide.inc";

SUBDESIGN hbars(   
	VAC[10..0]			: INPUT;
	clk			    	: INPUT;
	
	blocksize[6..0]		: INPUT;
	v_sta[11..0]	    : INPUT;
	v_end[11..0]	    : INPUT;
	act_vcounter[10..0]	: INPUT;
	vposition[10..0]    : INPUT;
	
	venable            : OUTPUT;
)

VARIABLE
	vposition_shift_vac
	           : lpm_add_sub WITH (
				                    LPM_WIDTH = 12,
				                    --LPM_DIRECTION = "ADD", --1-add,0-sub
				                    ONE_INPUT_IS_CONSTANT = "YES",
				                    LPM_PIPELINE = 0
				                    );
	vsta_add,
	vend_add			
	           : lpm_add_sub WITH (
				                    LPM_WIDTH = 12,
				                    LPM_DIRECTION = "ADD",
				                    ONE_INPUT_IS_CONSTANT = "NO",
				                    LPM_PIPELINE = 0
				                    );					
    vsta_module,
	vend_module
               : lpm_divide  WITH ( 
                                    LPM_WIDTHN = 12,
                                    LPM_WIDTHD = 12,
                                    LPM_TYPE = "LPM_DIVIDE",
                                    LPM_NREPRESENTATION = "UNSIGNED",
			                        LPM_HINT = "LPM_REMAINDERPOSITIVE=TRUE",
			                        LPM_DREPRESENTATION = "UNSIGNED",
			                        LPM_PIPELINE = 0
                                   );
    vload1, 
	vload2
     			: lpm_compare WITH (
				                    LPM_WIDTH = 11,
									ONE_INPUT_IS_CONSTANT = "YES",
									LPM_REPRESENTATION = "UNSIGNED",
									LPM_PIPELINE = 2
									);
    v_sta_end_compare
     			: lpm_compare WITH (
				                    LPM_WIDTH = 11,
									ONE_INPUT_IS_CONSTANT = "NO",
									LPM_REPRESENTATION = "UNSIGNED",
									LPM_PIPELINE = 0
									);
                  

	loadvsta[10..0],loadvend[10..0]            : NODE;
	--loadvsta_add[10..0],loadvend_add[10..0]    : NODE;
	--loadvsta_sub[10..0],loadvend_sub[10..0]    : NODE;
	v_enable                                   : DFFE;
	
BEGIN
    vposition_shift_vac.dataa[]=(0,VAC[]);
    vposition_shift_vac.datab[]=(0,0,vposition[9..0]);
    vposition_shift_vac.add_sub=vposition[10];

    vsta_add.dataa[]=v_sta[];
    vsta_add.datab[]=vposition_shift_vac.result[];    
    vend_add.dataa[]=v_end[];
    vend_add.datab[]=vposition_shift_vac.result[];

    vsta_module.numer[]=vsta_add.result[];
    vsta_module.denom[]=(0,VAC[]);
    vend_module.numer[]=vend_add.result[];
    vend_module.denom[]=(0,VAC[]);

    loadvsta[] = vsta_module.remain[10..0];
    loadvend[] = vend_module.remain[10..0];
    
    v_enable.clk=clk;
    CASE v_sta_end_compare.alb IS
    WHEN 1 => 
       v_enable.d = vload1.ageb AND vload2.alb;
    WHEN 0 =>
       v_enable.d = vload1.ageb OR  vload2.alb;
    END CASE;
   
    vload1.dataa[] = act_vcounter[];
    vload1.datab[] = loadvsta[];
    vload1.clock   = clk;
    vload2.dataa[] = act_vcounter[];
    vload2.datab[] = loadvend[];
    vload2.clock   = clk;

    v_sta_end_compare.dataa[]=loadvsta[];
    v_sta_end_compare.datab[]=loadvend[];


    CASE blocksize[6..0] IS
    WHEN 0 =>
         venable = GND;
    WHEN OTHERS =>
         venable = v_enable.q;        
    END CASE; 
	 

END;