pattern_dl.vhd

基于fpga的屏幕测试程序

LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.numeric_std.all;

ENTITY pattern_dl IS 
GENERIC(
	HAC		: integer  :=1280;
	VAC		: integer  :=1024;
	dataN   : integer  :=319;
	--HBLOCK  : integer  :=100;
	--VBLOCK  : integer  :=100;
	H_WIDTH : integer  :=1280;
	V_WIDTH : integer  :=1024;	
	HCE 	: integer  :=640;
	VCE 	: integer  :=512
	);

PORT( 
  clk     	: IN  std_logic;
  clken   	: IN  std_logic;		-- frame sync
  wren    	: IN  std_logic;		-- ram write enalbe
  hcount  	: IN  std_logic_vector(10 DOWNTO 0); 
  vcount  	: IN  std_logic_vector(10 DOWNTO 0); 
  data_length:  IN  std_logic_vector(13 DOWNTO 0);
  address   : IN  std_logic_vector(8 DOWNTO 0);	-- address of data via i2c
  date_r    : IN  std_logic_vector(7 DOWNTO 0);	-- data, with address via i2c
  date_g    : IN  std_logic_vector(7 DOWNTO 0);	
  date_b    : IN  std_logic_vector(7 DOWNTO 0);	

  trigger    : OUT std_logic;
  active     : OUT std_logic;	--no used
  red_out    : OUT std_logic_vector(7 DOWNTO 0);
  green_out  : OUT std_logic_vector(7 DOWNTO 0);
  blue_out   : OUT std_logic_vector(7 DOWNTO 0)
);

END pattern_dl;

ARCHITECTURE rtl OF pattern_dl IS

--SIGNAL counter			: INTEGER RANGE 511 DOWNTO 0 ;
SIGNAL counti			: STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL rdaddress_a		: STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL rdaddress_b		: STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL start			: STD_LOGIC;

SIGNAL red_ram_qa		: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL red_ram_qb		: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL green_ram_qa		: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL green_ram_qb		: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL blue_ram_qa		: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL blue_ram_qb		: STD_LOGIC_VECTOR(7 DOWNTO 0);


COMPONENT data_red IS PORT --port b is reserved
(
	data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
	wraddress	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
	rdaddress_a	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
	rdaddress_b	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
	wren		: IN STD_LOGIC  := '1';
	clock		: IN STD_LOGIC ;
	qa		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
	qb		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;

COMPONENT data_green IS PORT
(
	data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
	wraddress	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
	rdaddress_a	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
	rdaddress_b	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
	wren		: IN STD_LOGIC  := '1';
	clock		: IN STD_LOGIC ;
	qa		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
	qb		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;

COMPONENT data_blue IS PORT
(
	data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
	wraddress	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
	rdaddress_a	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
	rdaddress_b	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
	wren		: IN STD_LOGIC  := '1';
	clock		: IN STD_LOGIC ;
	qa		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
	qb		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;

BEGIN
		
-- buffer for data downloaded via i2c
dr: data_red PORT MAP
	(  
		data		=>	date_r,
		wraddress	=>	address,
		rdaddress_a	=>	rdaddress_a,
		rdaddress_b	=>	rdaddress_b,
		wren		=>	wren,
		clock		=>	clk,
		qa	=>	red_ram_qa,
		qb	=>	red_ram_qb
	);
	
dg: data_green PORT MAP
	(  
		data		=>	date_g,
		wraddress	=>	address,
		rdaddress_a	=>	rdaddress_a,
		rdaddress_b	=>	rdaddress_b,
		wren		=>	wren,
		clock		=>	clk,
		qa	=>	green_ram_qa,
		qb	=>	green_ram_qb
	);
	
db: data_blue PORT MAP
	(  
		data		=>	date_b,
		wraddress	=>	address,
		rdaddress_a	=>	rdaddress_a,
		rdaddress_b	=>	rdaddress_b,
		wren		=>	wren,
		clock		=>	clk,
		qa	=>	blue_ram_qa,
		qb	=>	blue_ram_qb
	);		

PROCESS(clk, clken)
BEGIN
	IF clken='1' THEN
		if counti < data_length then 
			counti <= counti+1;
		 else 
			counti <= (others =>'0');
		end if;
		
		if counti =  "000000000" then
			start <= '1';
		 else
			start <= '0';
		end if; 	
	END IF; 	
END PROCESS;

PROCESS(clk, counti)
BEGIN
IF clk'event AND clk='1' THEN
	rdaddress_a <= counti;
	rdaddress_b <= counti;
END IF;
END PROCESS;

PROCESS(clk,hcount,vcount)
BEGIN
IF clk'event AND clk='1' THEN
	if vcount>=VCE-V_WIDTH AND vcount<VCE+V_WIDTH AND 
	   hcount>=HCE-H_WIDTH AND hcount<HCE+H_WIDTH THEN
		active <= '1';
	else active <= '0';
	end if; 
END IF;
END PROCESS;

PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
CASE wren IS
	WHEN '0' =>
	red_out <= red_ram_qa;
	green_out <= green_ram_qa;
	blue_out <= blue_ram_qa;
	trigger <= start;
	WHEN OTHERS =>
	red_out <= (others =>'0');
	green_out <= (others =>'0');
	blue_out <= (others =>'0');
	trigger <= '0';	
END CASE;
END IF;
END PROCESS;


END rtl;