frantic_patgen_wvga.acf
来自「基于fpga的屏幕测试程序」· ACF 代码 · 共 720 行 · 第 1/2 页
ACF
720 行
--
-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
--
CHIP frantic_patgen_WVGA
BEGIN
|Green_out9 : OUTPUT_PIN = 151;
|Red0 : INPUT_PIN = 6;
|Red1 : INPUT_PIN = 7;
|Red2 : INPUT_PIN = 8;
|Red3 : INPUT_PIN = 9;
|Red4 : INPUT_PIN = 11;
|Red5 : INPUT_PIN = 12;
|Red6 : INPUT_PIN = 13;
|Red7 : INPUT_PIN = 14;
|Red8 : INPUT_PIN = 15;
|Red9 : INPUT_PIN = 17;
|Green0 : INPUT_PIN = 23;
|Green1 : INPUT_PIN = 24;
|Green2 : INPUT_PIN = 25;
|Green3 : INPUT_PIN = 26;
|Green4 : INPUT_PIN = 28;
|Green5 : INPUT_PIN = 29;
|Green6 : INPUT_PIN = 30;
|Green7 : INPUT_PIN = 31;
|Green8 : INPUT_PIN = 33;
|Green9 : INPUT_PIN = 34;
|Blue0 : INPUT_PIN = 35;
|Blue1 : INPUT_PIN = 36;
|Blue2 : INPUT_PIN = 38;
|Blue3 : INPUT_PIN = 39;
|Blue4 : INPUT_PIN = 40;
|Blue5 : INPUT_PIN = 41;
|Blue6 : INPUT_PIN = 43;
|Blue7 : INPUT_PIN = 44;
|Blue8 : INPUT_PIN = 45;
|Blue9 : INPUT_PIN = 46;
|Hsync : INPUT_PIN = 94;
|Vsync : INPUT_PIN = 95;
|NBLANKin : INPUT_PIN = 97;
|Hsync_display : OUTPUT_PIN = 134;
|Vsync_display : OUTPUT_PIN = 133;
|Nblank_display : OUTPUT_PIN = 132;
|enable_display : OUTPUT_PIN = 131;
|Field_ident : OUTPUT_PIN = 129;
|Red_out0 : OUTPUT_PIN = 174;
|Red_out1 : OUTPUT_PIN = 173;
|Red_out2 : OUTPUT_PIN = 172;
|Red_out3 : OUTPUT_PIN = 171;
|Red_out4 : OUTPUT_PIN = 169;
|Red_out5 : OUTPUT_PIN = 168;
|Red_out6 : OUTPUT_PIN = 167;
|Red_out7 : OUTPUT_PIN = 166;
|Red_out8 : OUTPUT_PIN = 164;
|Red_out9 : OUTPUT_PIN = 163;
|Green_out0 : OUTPUT_PIN = 162;
|Green_out1 : OUTPUT_PIN = 161;
|Green_out2 : OUTPUT_PIN = 159;
|Green_out3 : OUTPUT_PIN = 158;
|Green_out4 : OUTPUT_PIN = 157;
|Green_out5 : OUTPUT_PIN = 156;
|Green_out6 : OUTPUT_PIN = 154;
|Green_out7 : OUTPUT_PIN = 153;
|Green_out8 : OUTPUT_PIN = 152;
|Blue_out0 : OUTPUT_PIN = 149;
|Blue_out1 : OUTPUT_PIN = 148;
|Blue_out2 : OUTPUT_PIN = 147;
|Blue_out3 : OUTPUT_PIN = 146;
|Blue_out4 : OUTPUT_PIN = 144;
|Blue_out5 : OUTPUT_PIN = 143;
|Blue_out6 : OUTPUT_PIN = 142;
|Blue_out7 : OUTPUT_PIN = 141;
|Blue_out8 : OUTPUT_PIN = 139;
|Blue_out9 : OUTPUT_PIN = 138;
|Xpander7 : INPUT_PIN = 119;
|Xpander5 : INPUT_PIN = 90;
|Xpander4 : INPUT_PIN = 117;
|Xpander3 : INPUT_PIN = 120;
|Xpander2 : INPUT_PIN = 211;
|Xpander1 : INPUT_PIN = 92;
|Xpander0 : INPUT_PIN = 210;
|Xpander6 : INPUT_PIN = 118;
|SDA_in : INPUT_PIN = 212;
|SCL_in : INPUT_PIN = 137;
|DISPEN : INPUT_PIN = 55;
|parity_in : INPUT_PIN = 54;
|HQ_en : INPUT_PIN = 128;
|HQ_enable : OUTPUT_PIN = 18;
|test3 : BIDIR_PIN = 107;
|test4 : BIDIR_PIN = 108;
|test5 : BIDIR_PIN = 109;
|clock : INPUT_PIN = 91;
|SDA_out : OUTPUT_PIN = 231;
|HiBrite : OUTPUT_PIN = 181;
DEVICE = EPF10K100EQC240-2;
|CPUGO : OUTPUT_PIN = 82;
|PDPGO : OUTPUT_PIN = 83;
|IRQ : OUTPUT_PIN = 84;
|PWDN : OUTPUT_PIN = 61;
|SCLO : INPUT_PIN = 80;
|SDAO : INPUT_PIN = 81;
|dumsda : INPUT_PIN = 65;
|dumscl : INPUT_PIN = 63;
END;
DEFAULT_DEVICES
BEGIN
AUTO_DEVICE = EPF10K30ETC144-1;
AUTO_DEVICE = EPF10K30EQC208-1;
AUTO_DEVICE = EPF10K30EFC256-1;
AUTO_DEVICE = EPF10K30EFC484-1;
AUTO_DEVICE = EPF10K50ETC144-1;
AUTO_DEVICE = EPF10K50EQC208-1;
AUTO_DEVICE = EPF10K50EQC240-1;
AUTO_DEVICE = EPF10K50EFC256-1;
AUTO_DEVICE = EPF10K50EFC484-1;
AUTO_DEVICE = EPF10K100EQC208-1;
AUTO_DEVICE = EPF10K100EQC240-1;
AUTO_DEVICE = EPF10K100EBC356-1;
AUTO_DEVICE = EPF10K100EFC484-1;
AUTO_DEVICE = EPF10K130EQC240-1;
AUTO_DEVICE = EPF10K130EFC484-1;
AUTO_DEVICE = EPF10K130EFC672-1;
AUTO_DEVICE = EPF10K200EBC600-1;
AUTO_DEVICE = EPF10K200EFC672-1;
ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
END;
TIMING_POINT
BEGIN
DEVICE_FOR_TIMING_SYNTHESIS = EPF10K100EQC240-2;
MAINTAIN_STABLE_SYNTHESIS = ON;
CUT_ALL_BIDIR = ON;
CUT_ALL_CLEAR_PRESET = ON;
END;
IGNORED_ASSIGNMENTS
BEGIN
IGNORE_CLIQUE_ASSIGNMENTS = OFF;
IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
IGNORE_TIMING_ASSIGNMENTS = OFF;
IGNORE_CHIP_ASSIGNMENTS = OFF;
IGNORE_PIN_ASSIGNMENTS = OFF;
IGNORE_LC_ASSIGNMENTS = OFF;
IGNORE_DEVICE_ASSIGNMENTS = OFF;
IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
FIT_IGNORE_TIMING = ON;
END;
GLOBAL_PROJECT_DEVICE_OPTIONS
BEGIN
MAX7000B_ENABLE_VREFB = OFF;
MAX7000B_ENABLE_VREFA = OFF;
MAX7000B_VCCIO_IOBANK2 = 3.3V;
MAX7000B_VCCIO_IOBANK1 = 3.3V;
FLEX_CONFIGURATION_EPROM = EPC1PC8;
CONFIG_EPROM_PULLUP_RESISTOR = ON;
CONFIG_EPROM_USER_CODE = FFFFFFFF;
RESERVED_LCELLS_PERCENT = 0;
RESERVED_PINS_PERCENT = 0;
SECURITY_BIT = OFF;
USER_CLOCK = OFF;
AUTO_RESTART = OFF;
RELEASE_CLEARS = OFF;
ENABLE_DCLK_OUTPUT = OFF;
DISABLE_TIME_OUT = OFF;
CONFIG_SCHEME = ACTIVE_SERIAL;
FLEX8000_ENABLE_JTAG = OFF;
DATA0 = RESERVED_TRI_STATED;
DATA1_TO_DATA7 = UNRESERVED;
nWS_nRS_nCS_CS = UNRESERVED;
RDYnBUSY = UNRESERVED;
RDCLK = UNRESERVED;
SDOUT = RESERVED_DRIVES_OUT;
ADD0_TO_ADD12 = UNRESERVED;
ADD13 = UNRESERVED;
ADD14 = UNRESERVED;
ADD15 = UNRESERVED;
ADD16 = UNRESERVED;
ADD17 = UNRESERVED;
CLKUSR = UNRESERVED;
nCEO = UNRESERVED;
ENABLE_CHIP_WIDE_RESET = OFF;
ENABLE_CHIP_WIDE_OE = OFF;
ENABLE_INIT_DONE_OUTPUT = OFF;
FLEX10K_JTAG_USER_CODE = 7F;
CONFIG_SCHEME_10K = PASSIVE_SERIAL;
MAX7000S_USER_CODE = FFFF;
FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
MAX7000S_ENABLE_JTAG = ON;
MULTIVOLT_IO = OFF;
CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
FLEX6000_ENABLE_JTAG = OFF;
FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
MAX7000AE_USER_CODE = FFFFFFFF;
MAX7000AE_ENABLE_JTAG = ON;
END;
GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
BEGIN
DEVICE_FAMILY = FLEX10KE;
STYLE = WYSIWYG;
MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
AUTO_GLOBAL_CLOCK = ON;
AUTO_GLOBAL_CLEAR = ON;
AUTO_GLOBAL_PRESET = ON;
AUTO_GLOBAL_OE = ON;
AUTO_FAST_IO = OFF;
AUTO_REGISTER_PACKING = OFF;
ONE_HOT_STATE_MACHINE_ENCODING = OFF;
AUTO_OPEN_DRAIN_PINS = ON;
AUTO_IMPLEMENT_IN_EAB = OFF;
MULTI_LEVEL_SYNTHESIS_MAX9000 = ON;
OPTIMIZE_FOR_SPEED = 10;
END;
COMPILER_PROCESSING_CONFIGURATION
BEGIN
DESIGN_DOCTOR = OFF;
DESIGN_DOCTOR_RULES = EPLD;
FUNCTIONAL_SNF_EXTRACTOR = OFF;
TIMING_SNF_EXTRACTOR = ON;
OPTIMIZE_TIMING_SNF = OFF;
LINKED_SNF_EXTRACTOR = OFF;
RPT_FILE_EQUATIONS = ON;
RPT_FILE_HIERARCHY = ON;
RPT_FILE_LCELL_INTERCONNECT = ON;
RPT_FILE_USER_ASSIGNMENTS = ON;
GENERATE_AHDL_TDO_FILE = OFF;
SMART_RECOMPILE = OFF;
FITTER_SETTINGS = NORMAL;
PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF;
END;
COMPILER_INTERFACES_CONFIGURATION
BEGIN
VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
VERILOG_FLATTEN_BUS = OFF;
VHDL_FLATTEN_BUS = OFF;
VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
EDIF_INPUT_LMF1 = *.lmf;
EDIF_INPUT_LMF2 = *.lmf;
EDIF_OUTPUT_EDC_FILE = *.edc;
EDIF_INPUT_VCC = VCC;
EDIF_INPUT_GND = GND;
EDIF_OUTPUT_VCC = VCC;
EDIF_OUTPUT_GND = GND;
EDIF_INPUT_USE_LMF1 = OFF;
EDIF_INPUT_USE_LMF2 = OFF;
EDIF_OUTPUT_USE_EDC = OFF;
EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
EDIF_FLATTEN_BUS = OFF;
EDIF_BUS_DELIMITERS = [];
EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
EDIF_NETLIST_WRITER = OFF;
EDIF_OUTPUT_VERSION = 200;
XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
XNF_GENERATE_AHDL_TDX_FILE = ON;
VERILOG_NETLIST_WRITER = OFF;
VHDL_NETLIST_WRITER = OFF;
USE_SYNOPSYS_SYNTHESIS = OFF;
SYNOPSYS_COMPILER = DESIGN;
SYNOPSYS_DESIGNWARE = OFF;
SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
SYNOPSYS_MAPPING_EFFORT = MEDIUM;
VHDL_READER_VERSION = VHDL87;
VHDL_WRITER_VERSION = VHDL87;
END;
CUSTOM_DESIGN_DOCTOR_RULES
BEGIN
RIPPLE_CLOCKS = ON;
GATED_CLOCKS = ON;
MULTI_LEVEL_CLOCKS = ON;
MULTI_CLOCK_NETWORKS = ON;
STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
PRESET_CLEAR_NETWORKS = ON;
ASYNCHRONOUS_INPUTS = ON;
DELAY_CHAINS = ON;
RACE_CONDITIONS = ON;
EXPANDER_NETWORKS = ON;
MASTER_RESET = OFF;
END;
SIMULATOR_CONFIGURATION
BEGIN
END_TIME = 300.0us;
BIDIR_PIN = STRONG;
USE_DEVICE = OFF;
SETUP_HOLD = OFF;
CHECK_OUTPUTS = OFF;
OSCILLATION = OFF;
OSCILLATION_TIME = 0.0ns;
GLITCH = OFF;
GLITCH_TIME = 0.0ns;
START_TIME = 0.0ns;
END;
TIMING_ANALYZER_CONFIGURATION
BEGIN
|fullregbuf45.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf44.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf43.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf42.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf41.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf40.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf39.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf38.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf37.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf36.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf35.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf34.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf33.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf32.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf31.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf30.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf29.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf28.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf27.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf26.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf25.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf24.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf23.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf22.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf21.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf20.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf19.Q : REGISTERED_PERFORMANCE_CUTOFF;
|fullregbuf18.Q : REGISTERED_PERFORMANCE_CUTOFF;
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?