cyclic.csf
来自「基于fpga的屏幕测试程序」· CSF 代码 · 共 717 行 · 第 1/2 页
CSF
717 行
data[2] : IO_STANDARD = "SSTL-2 CLASS II";
data[20] : LOCATION = Pin_N14;
data[20] : IO_STANDARD = "SSTL-2 CLASS II";
data[21] : LOCATION = Pin_P14;
data[21] : IO_STANDARD = "SSTL-2 CLASS II";
data[22] : LOCATION = Pin_P17;
data[22] : IO_STANDARD = "SSTL-2 CLASS II";
data[23] : LOCATION = Pin_R15;
data[23] : IO_STANDARD = "SSTL-2 CLASS II";
data[24] : LOCATION = Pin_D18;
data[24] : IO_STANDARD = "SSTL-2 CLASS II";
data[25] : LOCATION = Pin_E15;
data[25] : IO_STANDARD = "SSTL-2 CLASS II";
data[26] : LOCATION = Pin_E16;
data[26] : IO_STANDARD = "SSTL-2 CLASS II";
data[27] : LOCATION = Pin_F15;
data[27] : IO_STANDARD = "SSTL-2 CLASS II";
data[28] : LOCATION = Pin_G13;
data[28] : IO_STANDARD = "SSTL-2 CLASS II";
data[29] : LOCATION = Pin_G17;
data[29] : IO_STANDARD = "SSTL-2 CLASS II";
data[3] : LOCATION = Pin_U7;
data[3] : IO_STANDARD = "SSTL-2 CLASS II";
data[30] : LOCATION = Pin_G18;
data[30] : IO_STANDARD = "SSTL-2 CLASS II";
data[31] : LOCATION = Pin_H18;
data[31] : IO_STANDARD = "SSTL-2 CLASS II";
data[4] : LOCATION = Pin_P6;
data[4] : IO_STANDARD = "SSTL-2 CLASS II";
data[5] : LOCATION = Pin_U6;
data[5] : IO_STANDARD = "SSTL-2 CLASS II";
data[6] : LOCATION = Pin_U5;
data[6] : IO_STANDARD = "SSTL-2 CLASS II";
data[7] : LOCATION = Pin_T5;
data[7] : IO_STANDARD = "SSTL-2 CLASS II";
data[8] : LOCATION = Pin_U15;
data[8] : IO_STANDARD = "SSTL-2 CLASS II";
data[9] : LOCATION = Pin_V15;
data[9] : IO_STANDARD = "SSTL-2 CLASS II";
tp[1] : LOCATION = Pin_F16;
tp[1] : IO_STANDARD = LVCMOS;
tp[2] : LOCATION = Pin_R8;
tp[2] : IO_STANDARD = LVCMOS;
tp[3] : LOCATION = Pin_P10;
tp[3] : IO_STANDARD = LVCMOS;
tp[4] : LOCATION = Pin_R11;
tp[4] : IO_STANDARD = LVCMOS;
tp[5] : LOCATION = Pin_T13;
tp[5] : IO_STANDARD = LVCMOS;
tp[6] : LOCATION = Pin_P7;
tp[6] : IO_STANDARD = LVCMOS;
tp[7] : LOCATION = Pin_R10;
tp[7] : IO_STANDARD = LVCMOS;
tp[8] : LOCATION = Pin_P12;
tp[8] : IO_STANDARD = LVCMOS;
tp[9] : LOCATION = Pin_R13;
tp[9] : IO_STANDARD = LVCMOS;
tp[10] : LOCATION = Pin_F14;
tp[10] : IO_STANDARD = LVCMOS;
tp[11] : LOCATION = Pin_G5;
tp[11] : IO_STANDARD = LVCMOS;
tp[12] : LOCATION = Pin_G4;
tp[12] : IO_STANDARD = LVCMOS;
tp[13] : LOCATION = Pin_N6;
tp[13] : IO_STANDARD = LVCMOS;
tp[14] : LOCATION = Pin_F7;
tp[14] : IO_STANDARD = LVCMOS;
tp[15] : LOCATION = Pin_B4;
tp[15] : IO_STANDARD = LVCMOS;
tp[16] : LOCATION = Pin_F12;
tp[16] : IO_STANDARD = LVCMOS;
tp[17] : LOCATION = Pin_N15;
tp[17] : IO_STANDARD = LVCMOS;
tp[18] : LOCATION = Pin_N12;
tp[18] : IO_STANDARD = LVCMOS;
clkn1 : LOCATION = Pin_K16;
clkp1 : LOCATION = Pin_K15;
clkn2 : LOCATION = Pin_K5;
clkp2 : LOCATION = Pin_K4;
pdpgoo : LOCATION = Pin_B7;
pdpgoo : IO_STANDARD = LVCMOS;
cpugoo : LOCATION = Pin_D7;
cpugoo : IO_STANDARD = LVCMOS;
clk_out1 : LOCATION = Pin_B14;
clk_out1 : IO_STANDARD = LVCMOS;
clk_out2 : LOCATION = Pin_B5;
clk_out2 : IO_STANDARD = LVCMOS;
dclk : LOCATION = Pin_J3;
clk1 : LOCATION = Pin_J4;
clk2 : LOCATION = Pin_J15;
clk3 : LOCATION = Pin_J16;
pdwno : LOCATION = Pin_E5;
pdwno : IO_STANDARD = LVCMOS;
cpugoi : LOCATION = Pin_L4;
cpugoi : IO_STANDARD = LVCMOS;
pdpgoi : LOCATION = Pin_L7;
pdpgoi : IO_STANDARD = LVCMOS;
oei : LOCATION = Pin_G3;
oei : IO_STANDARD = LVCMOS;
de_in : LOCATION = Pin_R1;
de_in : IO_STANDARD = LVCMOS;
hsync_in : LOCATION = Pin_P4;
hsync_in : IO_STANDARD = LVCMOS;
vsync_in : LOCATION = Pin_P5;
vsync_in : IO_STANDARD = LVCMOS;
pdwni : LOCATION = Pin_G2;
pdwni : IO_STANDARD = LVCMOS;
asd : LOCATION = Pin_J1;
asd : IO_STANDARD = LVCMOS;
ncs : LOCATION = Pin_K6;
ncs : IO_STANDARD = LVCMOS;
rs232_rx : LOCATION = Pin_E2;
rs232_rx : IO_STANDARD = LVCMOS;
rs232_tx : LOCATION = Pin_D1;
rs232_tx : IO_STANDARD = LVCMOS;
de_out : LOCATION = Pin_N13;
de_out : IO_STANDARD = LVCMOS;
de_out_1 : LOCATION = Pin_D15;
de_out_1 : IO_STANDARD = LVCMOS;
dm0 : LOCATION = Pin_R9;
dm0 : IO_STANDARD = "SSTL-2 CLASS II";
dm1 : LOCATION = Pin_U11;
dm1 : IO_STANDARD = "SSTL-2 CLASS II";
dm2 : LOCATION = Pin_L16;
dm2 : IO_STANDARD = "SSTL-2 CLASS II";
dm3 : LOCATION = Pin_H13;
dm3 : IO_STANDARD = "SSTL-2 CLASS II";
dqs0 : LOCATION = Pin_R4;
dqs0 : IO_STANDARD = "SSTL-2 CLASS II";
dqs1 : LOCATION = Pin_U14;
dqs1 : IO_STANDARD = "SSTL-2 CLASS II";
dqs2 : LOCATION = Pin_P15;
dqs2 : IO_STANDARD = "SSTL-2 CLASS II";
dqs3 : LOCATION = Pin_E17;
dqs3 : IO_STANDARD = "SSTL-2 CLASS II";
hsync_out : LOCATION = Pin_F13;
hsync_out : IO_STANDARD = LVCMOS;
hsync_out_1 : LOCATION = Pin_L13;
hsync_out_1 : IO_STANDARD = LVCMOS;
parity_out_o : LOCATION = Pin_G15;
parity_out_o : IO_STANDARD = LVCMOS;
parity_out_e : LOCATION = Pin_D17;
parity_out_e : IO_STANDARD = LVCMOS;
te_6_1 : LOCATION = Pin_M13;
te_6_1 : IO_STANDARD = LVCMOS;
te_6_2 : LOCATION = Pin_L15;
te_6_2 : IO_STANDARD = LVCMOS;
irq : LOCATION = Pin_G6;
irq : IO_STANDARD = LVCMOS;
pixs_out : LOCATION = Pin_G14;
pixs_out : IO_STANDARD = LVCMOS;
ras1 : LOCATION = Pin_T9;
ras1 : IO_STANDARD = "SSTL-2 CLASS II";
ras2 : LOCATION = Pin_H14;
ras2 : IO_STANDARD = "SSTL-2 CLASS II";
scl_pld : LOCATION = Pin_T6;
scl_pld : IO_STANDARD = LVCMOS;
sda_pld : LOCATION = Pin_T4;
sda_pld : IO_STANDARD = LVCMOS;
vref1 : LOCATION = Pin_P16;
vref1 : IO_STANDARD = 1.5V;
vsync_out : LOCATION = Pin_G12;
vsync_out : IO_STANDARD = LVCMOS;
vsync_out_1 : LOCATION = Pin_J13;
vsync_out_1 : IO_STANDARD = LVCMOS;
we1 : LOCATION = Pin_T8;
we1 : IO_STANDARD = "SSTL-2 CLASS II";
we2 : LOCATION = Pin_N17;
we2 : IO_STANDARD = "SSTL-2 CLASS II";
vref2 : LOCATION = Pin_E14;
vref2 : IO_STANDARD = 1.5V;
vref3 : LOCATION = Pin_J14;
vref3 : IO_STANDARD = 1.5V;
vref4 : LOCATION = Pin_P13;
vref4 : IO_STANDARD = 1.5V;
vref5 : LOCATION = Pin_P9;
vref5 : IO_STANDARD = 1.5V;
vref6 : LOCATION = Pin_R5;
vref6 : IO_STANDARD = 1.5V;
ba0 : RESERVE_PIN = "AS INPUT TRI-STATED";
ba1 : RESERVE_PIN = "AS INPUT TRI-STATED";
ba2 : RESERVE_PIN = "AS INPUT TRI-STATED";
ba3 : RESERVE_PIN = "AS INPUT TRI-STATED";
cas1 : RESERVE_PIN = "AS INPUT TRI-STATED";
cas2 : RESERVE_PIN = "AS INPUT TRI-STATED";
cke1 : RESERVE_PIN = "AS INPUT TRI-STATED";
cke2 : RESERVE_PIN = "AS INPUT TRI-STATED";
cso1 : RESERVE_PIN = "AS INPUT TRI-STATED";
cso2 : RESERVE_PIN = "AS INPUT TRI-STATED";
dm0 : RESERVE_PIN = "AS INPUT TRI-STATED";
dm1 : RESERVE_PIN = "AS INPUT TRI-STATED";
dm2 : RESERVE_PIN = "AS INPUT TRI-STATED";
dm3 : RESERVE_PIN = "AS INPUT TRI-STATED";
dqs0 : RESERVE_PIN = "AS INPUT TRI-STATED";
dqs1 : RESERVE_PIN = "AS INPUT TRI-STATED";
dqs2 : RESERVE_PIN = "AS INPUT TRI-STATED";
dqs3 : RESERVE_PIN = "AS INPUT TRI-STATED";
irq : RESERVE_PIN = "AS INPUT TRI-STATED";
ras1 : RESERVE_PIN = "AS INPUT TRI-STATED";
ras2 : RESERVE_PIN = "AS INPUT TRI-STATED";
we1 : RESERVE_PIN = "AS INPUT TRI-STATED";
we2 : RESERVE_PIN = "AS INPUT TRI-STATED";
STRATIX_DEVICE_IO_STANDARD = LVCMOS;
}
COMPILER_SETTINGS
{
IO_PLACEMENT_OPTIMIZATION = ON;
ENABLE_DRC_SETTINGS = OFF;
PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF;
PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF;
PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF;
DRC_FANOUT_EXCEEDING = 30;
DRC_REPORT_FANOUT_EXCEEDING = OFF;
DRC_TOP_FANOUT = 50;
DRC_REPORT_TOP_FANOUT = OFF;
RUN_DRC_DURING_COMPILATION = OFF;
ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON;
ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF;
ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF;
ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF;
SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF;
MERGE_HEX_FILE = OFF;
TRUE_WYSIWYG_FLOW = OFF;
SEED = 1;
FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY;
FAMILY = Cyclone;
DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1";
DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1";
DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB";
DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3";
DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4";
DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3";
DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS";
DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS";
DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS";
STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2";
STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1";
FAST_FIT_COMPILATION = OFF;
SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF;
DISABLE_PLL_COMPENSATION_DELAY_CHANGE_WARNING = OFF;
OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON;
OPTIMIZE_TIMING = NORMAL_COMPILATION;
OPTIMIZE_HOLD_TIMING = "IO PATHS AND MINIMUM TPD PATHS";
COMPILATION_LEVEL = FULL;
SAVE_DISK_SPACE = ON;
SPEED_DISK_USAGE_TRADEOFF = NORMAL;
LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF;
SIGNALPROBE_ALLOW_OVERUSE = OFF;
FOCUS_ENTITY_NAME = |cyclic;
}
DEFAULT_DEVICE_OPTIONS
{
GENERATE_CONFIG_HEXOUT_FILE = OFF;
GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON;
GENERATE_CONFIG_JBC_FILE = OFF;
GENERATE_CONFIG_JAM_FILE = OFF;
GENERATE_CONFIG_ISC_FILE = OFF;
GENERATE_CONFIG_SVF_FILE = OFF;
GENERATE_JBC_FILE_COMPRESSED = ON;
GENERATE_JBC_FILE = OFF;
GENERATE_JAM_FILE = OFF;
GENERATE_ISC_FILE = OFF;
GENERATE_SVF_FILE = OFF;
RESERVE_PIN = "AS INPUT TRI-STATED";
RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND";
HEXOUT_FILE_COUNT_DIRECTION = UP;
HEXOUT_FILE_START_ADDRESS = 0;
GENERATE_HEX_FILE = OFF;
GENERATE_RBF_FILE = OFF;
GENERATE_TTF_FILE = OFF;
RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED";
RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO";
RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO";
RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO";
DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF;
AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
STRATIX_CONFIGURATION_DEVICE = AUTO;
CYCLONE_CONFIGURATION_DEVICE = AUTO;
FLEX10K_CONFIGURATION_DEVICE = AUTO;
FLEX6K_CONFIGURATION_DEVICE = AUTO;
MERCURY_CONFIGURATION_DEVICE = AUTO;
EXCALIBUR_CONFIGURATION_DEVICE = AUTO;
APEX20K_CONFIGURATION_DEVICE = AUTO;
USE_CONFIGURATION_DEVICE = ON;
ENABLE_INIT_DONE_OUTPUT = OFF;
FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
ENABLE_DEVICE_WIDE_OE = OFF;
ENABLE_DEVICE_WIDE_RESET = OFF;
RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
AUTO_RESTART_CONFIGURATION = OFF;
ENABLE_VREFB_PIN = OFF;
ENABLE_VREFA_PIN = OFF;
SECURITY_BIT = OFF;
USER_START_UP_CLOCK = OFF;
APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL";
STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
STRATIX_UPDATE_MODE = STANDARD;
USE_CHECKSUM_AS_USERCODE = OFF;
MAX7000_USE_CHECKSUM_AS_USERCODE = OFF;
MAX7000_JTAG_USER_CODE = FFFFFFFF;
FLEX10K_JTAG_USER_CODE = 7F;
MERCURY_JTAG_USER_CODE = FFFFFFFF;
APEX20K_JTAG_USER_CODE = FFFFFFFF;
STRATIX_JTAG_USER_CODE = FFFFFFFF;
MAX7000S_JTAG_USER_CODE = FFFF;
RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
ENABLE_JTAG_BST_SUPPORT = OFF;
CONFIGURATION_CLOCK_DIVISOR = 1;
CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ";
CLOCK_SOURCE = INTERNAL;
COMPRESSION_MODE = OFF;
ON_CHIP_BITSTREAM_DECOMPRESSION = OFF;
}
AUTO_SLD_HUB_ENTITY
{
AUTO_INSERT_SLD_HUB_ENTITY = ENABLE;
HUB_INSTANCE_NAME = SLD_HUB_INST;
HUB_ENTITY_NAME = SLD_HUB;
}
SIGNALTAP_LOGIC_ANALYZER_SETTINGS
{
ENABLE_SIGNALTAP = Off;
AUTO_ENABLE_SMART_COMPILE = On;
}
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