vbars.tdf
来自「基于fpga的屏幕测试程序」· TDF 代码 · 共 118 行
TDF
118 行
-- vbars.tdf-- Based on Zhang Yuning's original work-- Reworked by Chai Lin-- 2006-08-27include "fran_pg.inc";include "lpm_rom.inc";include "lpm_compare.inc";include "lpm_add_sub.inc";include "lpm_divide.inc";SUBDESIGN vbars( HAC[10..0] : INPUT; clk : INPUT; blocksize[6..0] : INPUT; h_sta[11..0] : INPUT; h_end[11..0] : INPUT; act_hcounter[10..0] : INPUT; hposition[10..0] : INPUT; henable : OUTPUT;)VARIABLE hposition_shift_vac : lpm_add_sub WITH ( LPM_WIDTH = 12, --LPM_DIRECTION = "ADD", --1-add,0-sub ONE_INPUT_IS_CONSTANT = "YES", LPM_PIPELINE = 0 ); hsta_add, hend_add : lpm_add_sub WITH ( LPM_WIDTH = 12, LPM_DIRECTION = "ADD", ONE_INPUT_IS_CONSTANT = "NO", LPM_PIPELINE = 0 ); hsta_module_12b, hend_module_12b : lpm_divide WITH ( LPM_WIDTHN = 12, LPM_WIDTHD = 12, LPM_TYPE = "LPM_DIVIDE", LPM_NREPRESENTATION = "UNSIGNED", LPM_HINT = "LPM_REMAINDERPOSITIVE=TRUE", LPM_DREPRESENTATION = "UNSIGNED", LPM_PIPELINE = 0 ); hload1, hload2 : lpm_compare WITH ( LPM_WIDTH = 11, ONE_INPUT_IS_CONSTANT = "YES", LPM_REPRESENTATION = "UNSIGNED", LPM_PIPELINE = 2 ); h_sta_end_compare : lpm_compare WITH ( LPM_WIDTH = 11, ONE_INPUT_IS_CONSTANT = "NO", LPM_REPRESENTATION = "UNSIGNED", LPM_PIPELINE = 0 ); loadhsta[10..0],loadhend[10..0] : NODE; --loadhsta_add[10..0],loadhend_add[10..0] : NODE; --loadhsta_sub[10..0],loadhend_sub[10..0] : NODE; h_enable : DFFE; BEGIN hposition_shift_vac.dataa[]=(0,HAC[]); hposition_shift_vac.datab[]=(0,0,hposition[9..0]); hposition_shift_vac.add_sub=hposition[10]; hsta_add.dataa[]=h_sta[]; hsta_add.datab[]=hposition_shift_vac.result[]; hend_add.dataa[]=h_end[]; hend_add.datab[]=hposition_shift_vac.result[]; hsta_module_12b.numer[]=hsta_add.result[]; hsta_module_12b.denom[]=(0,HAC[]); hend_module_12b.numer[]=hend_add.result[]; hend_module_12b.denom[]=(0,HAC[]); loadhsta[] = hsta_module_12b.remain[10..0]; loadhend[] = hend_module_12b.remain[10..0]; h_enable.clk=clk; CASE h_sta_end_compare.alb IS WHEN 1 => h_enable.d = hload1.ageb AND hload2.alb; WHEN 0 => h_enable.d = hload1.ageb OR hload2.alb; END CASE; hload1.dataa[] = act_hcounter[]; hload1.datab[] = loadhsta[]; hload1.clock = clk; hload2.dataa[] = act_hcounter[]; hload2.datab[] = loadhend[]; hload2.clock = clk; h_sta_end_compare.dataa[]=loadhsta[]; h_sta_end_compare.datab[]=loadhend[]; CASE blocksize[6..0] IS WHEN 0 => henable = GND; WHEN OTHERS => henable = h_enable.q; END CASE; END;
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