cyclic.tan.summary

来自「基于fpga的屏幕测试程序」· SUMMARY 代码 · 共 117 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : 9.907 ns
Required Time  : 10.000 ns
Actual Time    : 0.093 ns
From           : b_e_i[7]
To             : input_buf_b_e[7]
From Clock     : 
To Clock       : dclk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : -2.974 ns
Required Time  : 10.000 ns
Actual Time    : 12.974 ns
From           : expander:i2c_expander|i2cSlave:I2Cslavecore_one|bitCounter[0]
To             : sda_pld
From Clock     : clk1_in
To Clock       : 
Failed Paths   : 10

Type           : Worst-case tpd
Slack          : -2.417 ns
Required Time  : 10.000 ns
Actual Time    : 12.417 ns
From           : tp_in[12]
To             : g_o_o[8]
From Clock     : 
To Clock       : 
Failed Paths   : 50

Type           : Worst-case th
Slack          : 4.430 ns
Required Time  : 10.000 ns
Actual Time    : 5.570 ns
From           : scl_pld
To             : expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sclMedian|sum[1]
From Clock     : 
To Clock       : clk1_in
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 6.931 ns
From           : g_e_o_dl[5]
To             : g_e_o[5]
From Clock     : dclk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case Minimum tpd
Slack          : N/A
Required Time  : None
Actual Time    : 6.016 ns
From           : clk1_in
To             : clk_out1
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'clk1_in'
Slack          : -15.774 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : 38.80 MHz ( period = 25.774 ns )
From           : fran_pg:pattern_generator|start_v_delay~3
To             : fran_pg:pattern_generator|pattern_dl:thepattern_dl|trigger~14
From Clock     : clk1_in
To Clock       : clk1_in
Failed Paths   : 4398

Type           : Clock Setup: 'dclk'
Slack          : 4.713 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : 189.14 MHz ( period = 5.287 ns )
From           : output_buf_b_e_dl[7]
To             : b_e_o_dl[9]
From Clock     : dclk
To Clock       : dclk
Failed Paths   : 0

Type           : Clock Hold: 'dclk'
Slack          : 0.663 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : N/A
From           : output_buf_g_e_dl[0]
To             : g_e_o_dl[0]
From Clock     : dclk
To Clock       : dclk
Failed Paths   : 0

Type           : Clock Hold: 'clk1_in'
Slack          : 0.794 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : N/A
From           : fran_pg:pattern_generator|serials:theserial|s3
To             : fran_pg:pattern_generator|serials:theserial|s3
From Clock     : clk1_in
To Clock       : clk1_in
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 4458

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