v_moving_blocks.tdf

来自「基于fpga的屏幕测试程序」· TDF 代码 · 共 210 行

-- h_moving_block.tdf
-- Yuning.Zhang, 2005-07-14
-- 


include "fran_pg.inc";
include "lpm_rom.inc";
include "lpm_compare";
include "lpm_counter.inc";

SUBDESIGN v_moving_blocks
(
	clk			    	: INPUT ;
	vout_pulse          : INPUT ;
	act_vcounter[10..0]	: INPUT ;
	act_hcounter[10..0] : INPUT ;

	v_position[7..0]    : INPUT ;   --first bit denotes position,verticle position, 
	velocity[4..0]      : INPUT ;   --First bit denotes direction;
	
	blocksize[4..0]	    : INPUT ;
	red_in[9..0]        : INPUT ;
	green_in[9..0]      : INPUT ;
	blue_in[9..0]       : INPUT ;     

	red_out[9..0]       : OUTPUT;
	green_out[9..0]     : OUTPUT;
	blue_out[9..0]      : OUTPUT;
)

VARIABLE
									
	hsta_table : LPM_ROM WITH (
				               LPM_WIDTH = 11,
				               LPM_WIDTHAD = 7,
				               LPM_ADDRESS_CONTROL = "REGISTERED",
			                   LPM_OUTDATA = "REGISTERED",
				               LPM_FILE = HSTA_TABLE_NAME
				               );
	hend_table : LPM_ROM WITH (
				               LPM_WIDTH = 11,
				               LPM_WIDTHAD = 7,
				               LPM_ADDRESS_CONTROL = "REGISTERED",
				               LPM_OUTDATA = "REGISTERED",
				               LPM_FILE = HEND_TABLE_NAME
				              );
	vsta_table : LPM_ROM WITH (
				               LPM_WIDTH = 11,
			                   LPM_WIDTHAD = 7,
				               LPM_ADDRESS_CONTROL = "REGISTERED",
				               LPM_OUTDATA = "REGISTERED",
				               LPM_FILE = VSTA_TABLE_NAME
				               );
	vend_table : LPM_ROM WITH (
				               LPM_WIDTH = 11,
				               LPM_WIDTHAD = 7,
				               LPM_ADDRESS_CONTROL = "REGISTERED",
				               LPM_OUTDATA = "REGISTERED",
				               LPM_FILE = VEND_TABLE_NAME
				               );
				
    vload1, vload2,
    hload1, hload2
     			: lpm_compare WITH (
				                    LPM_WIDTH = 11,
									ONE_INPUT_IS_CONSTANT = "YES",
									LPM_REPRESENTATION = "UNSIGNED",
									LPM_PIPELINE = 2
									);
									
	h_position : lpm_add_sub WITH (
				                    LPM_WIDTH = 10,
				                    LPM_DIRECTION = "ADD",
				                    ONE_INPUT_IS_CONSTANT = "NO",
				                    LPM_PIPELINE = 0
				                    );
				
	hsta_r,hend_r,vsta_u,vend_u
	           : lpm_add_sub WITH (
				                    LPM_WIDTH = 10,
				                    LPM_DIRECTION = "ADD",
				                    ONE_INPUT_IS_CONSTANT = "NO",
				                    LPM_PIPELINE = 0
				                    );
	
	hsta_l,hend_l,vsta_d,vend_d
	           : lpm_add_sub WITH (
				                    LPM_WIDTH = 10,
				                    LPM_DIRECTION = "SUB",
				                    ONE_INPUT_IS_CONSTANT = "NO",
				                    LPM_PIPELINE = 0
				                    );
	
	hloadblock,vloadblock	: SRFF;
	hsta[9..0],hend[9..0]   : NODE;              
	vsta[9..0],vend[9..0]   : NODE;
    h_enable,v_enable       : NODE;
	h_position_buffer[9..0] : DFFE;
	
BEGIN

    CASE  blocksize[2..0] IS
    WHEN 31      =>
	hsta_table.address[] = 102;
	hend_table.address[] = 102;
	vsta_table.address[] = 102;
	vend_table.address[] = 102;
	WHEN OTHERS =>
	hsta_table.address[] = (0,0,blocksize[4..0]);
	hend_table.address[] = (0,0,blocksize[4..0]);
	vsta_table.address[] = (0,0,blocksize[4..0]);
	vend_table.address[] = (0,0,blocksize[4..0]);	
	END CASE;
	
	h_position.dataa = (velocity[3..0]);
	h_position.datab = h_position_buffer[9..0];
	
	h_position_buffer.clk = clk;
	h_position_buffer.ena = vout_pulse;
	h_position_buffer.d   = h_position.rusult;
	
	hsta_table.inclock = clk;
	hend_table.inclock = clk;
	vsta_table.inclock = clk;
	vend_table.inclock = clk;

	hsta_table.outclock = clk;
	hend_table.outclock = clk;
	vsta_table.outclock = clk;
	vend_table.outclock = clk;
	
	----------------------------------------------------
	CASE v_position IS
	WHEN 0 =>
	     vsta = vsta_u.result;
	     vend = vend_u.result;
	WHEN 1 =>
	     vsta = vsta_d.result;
	     vend = vend_d.result;
	END CASE;
	
	CASE velocity[4] IS
	WHEN 0 =>
	     hsta = hsta_r.result;
	     hend = hsta_r.result;
	WHEN 1 =>
	     hsta = hsta_l.result;
	     hend = hend_l.result;
	END CASE;
	
	hsta_r.dataa[] = hsta_table.q[9..0];
	hend_r.dataa[] = hend_table.q[9..0];
	vsta_r.dataa[] = vsta_table.q[9..0];
	vend_r.dataa[] = vend_table.q[9..0];
	hsta_r.datab[] = h_position_buffer.q[9..0];
	hend_r.datab[] = h_position_buffer.q[9..0];
	vsta_r.datab[] = (v_position[6..0],0);
	vend_r.datab[] = (v_position[6..0],0);

    hsta_l.dataa[] = hsta_table.q[9..0];
	hend_l.dataa[] = hend_table.q[9..0];
	vsta_l.dataa[] = vsta_table.q[9..0];
	vend_l.dataa[] = vend_table.q[9..0];
	hsta_l.datab[] = h_position_buffer.q[9..0];
	hend_l.datab[] = h_position_buffer.q[9..0];
	vsta_l.datab[] = (v_position[6..0],0);
	vend_l.datab[] = (v_position[6..0],0);
	
	
    --------------------------------------------------------
    vload1.dataa[10..0] = act_vcounter[10..0];
    vload1.datab[10..0] = (0,vsta);
    vload1.clock = clk;

    vload2.dataa[10..0] = act_vcounter[10..0];
    vload2.datab[10..0] = (0,vend);
    vload2.clock = clk;

    --------------------------------------------------------
    hload1.dataa[10..0] = act_hcounter[10..0];
    hload1.datab[10..0] = hsta;
    hload1.clock = clk;

    hload2.dataa[10..0] = act_hcounter[10..0];
    hload2.datab[10..0] = hend;
    hload2.clock = clk;
   

    hloadblock.clk = clk;
    hloadblock.S   = hload1.aeb;
    hloadblock.R   = hload2.aeb;

    vloadblock.clk = clk;
    vloadblock.S   = vload1.aeb;
    vloadblock.R   = vload2.aeb;
    
    IF (blocksize) THEN
       h_enable = hloadblock.q;
       v_enable = vloadblock.q;        
    ELSE
       h_enable = GND;
       v_enable = GND;
    END IF;   

    red_out[]  = red_in[]  AND h_enable AND v_enable;
    green_out[]= green_in[]AND h_enable AND v_enable;
    blue_out[] = blue_in[] AND h_enable AND v_enable;

END;