dvi2lvds.vhd

来自「基于fpga的屏幕测试程序」· VHDL 代码 · 共 163 行

LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
--LIBRARY altera_mf;
--USE altera_mf.altera_mf_components.all;



--Eric Funke, started 17th August 2004;
--Yuning Zhang, 28th,July 2005;
-------------------------------------------------------------------
entity dvi2lvds is 
port(
	r_e_i			: 	in std_logic_vector(9 downto 0); 
	g_e_i			: 	in std_logic_vector(9 downto 0);	
	b_e_i			: 	in std_logic_vector(9 downto 0);
	dclk			:	in std_logic;
    de_in			:	in std_logic;
	hsync_in		:	in std_logic;
	vsync_in		:	in std_logic;	
			
	r_e_o			:	out std_logic_vector(9 downto 0);
	r_o_o			:	out std_logic_vector(9 downto 0);	
	g_e_o			:	out std_logic_vector(9 downto 0);
	g_o_o			:	out std_logic_vector(9 downto 0);	
	b_e_o			:	out std_logic_vector(9 downto 0);
	b_o_o			:	out std_logic_vector(9 downto 0);
		
			
	de_out			:	out std_logic;
	de_out_1		:	out std_logic;	
	hsync_out		:	out std_logic;
	hsync_out_1		:	out std_logic;	
	vsync_out		:	out std_logic;			
	vsync_out_1		:	out std_logic;			
	
	clk_out1 		:	out std_logic
);
 
end dvi2lvds;

architecture rtl of dvi2lvds is

	SIGNAL input_buf_r_e	:	std_logic_vector(9 downto 0);
	SIGNAL input_buf_g_e	:	std_logic_vector(9 downto 0);
	SIGNAL input_buf_b_e	:	std_logic_vector(9 downto 0);
	SIGNAL input_buf_hsync	:	std_logic;
	SIGNAL input_buf_vsync	:	std_logic;
	SIGNAL input_buf_de	    :	std_logic;
	SIGNAL input_var		:	std_logic;
	SIGNAL output_buf_r_e	:	std_logic_vector(9 downto 0);
	SIGNAL output_buf_g_e	:	std_logic_vector(9 downto 0);
	SIGNAL output_buf_b_e	:	std_logic_vector(9 downto 0);
	SIGNAL output_buf_r_o	:	std_logic_vector(9 downto 0);
	SIGNAL output_buf_g_o	:	std_logic_vector(9 downto 0);
	SIGNAL output_buf_b_o	:	std_logic_vector(9 downto 0);
	SIGNAL output_buf_hsync	:	std_logic;
	SIGNAL output_buf_vsync	:	std_logic;
	SIGNAL output_buf_de	:	std_logic;
	


	SIGNAL corrected_r_e_i		:	std_logic_vector(9 downto 0);
	SIGNAL thine_r_e_o			:	std_logic_vector(9 downto 0);	
	SIGNAL thine_g_e_o			:	std_logic_vector(9 downto 0);	
	SIGNAL thine_b_e_o			:	std_logic_vector(9 downto 0);		
	SIGNAL thine_r_o_o			:	std_logic_vector(9 downto 0);	
	SIGNAL thine_g_o_o			:	std_logic_vector(9 downto 0);	
	SIGNAL thine_b_o_o			:	std_logic_vector(9 downto 0);		
	SIGNAL thine_h,thine_v,thine_de		:	std_logic;
	SIGNAL old_de_in,h_count		:	std_logic;	
   	SIGNAL buffer_out_even,buffer_out_odd 	:	std_logic_vector(31 downto 0);
	SIGNAL buffer_in 			: 	std_logic_vector(31 downto 0);
	SIGNAL even_dvi_clk, odd_dvi_clk	:	std_logic;
	SIGNAL wrfull_even 			: 	std_logic;
	SIGNAL mem_aclr				:	std_logic;
	SIGNAL data_buf,data_buf2 		: 	std_logic_vector(31 downto 0);
	SIGNAL pll_is_locked			:	std_logic;
	SIGNAL pll_output			:	std_logic_vector(5 downto 0);
	SIGNAL reset_even,reset_odd		:	std_logic;
	SIGNAL old_vsync			:	std_logic;
	SIGNAL clk_out_split		:	std_logic;




begin


	process(dclk)
	begin
  	IF Rising_edge(dclk) THEN
  			
 			   			
		corrected_r_e_i <= (input_buf_r_e(7) & input_buf_r_e(9 DOWNTO 8) & input_buf_r_e(6 DOWNTO 0));
		
		thine_r_e_o <= (output_buf_r_e(7 downto 2) & output_buf_r_e(9 downto 8) & output_buf_r_e(1 DOWNTO 0));		
		thine_g_e_o <= (output_buf_g_e(7 downto 2) & output_buf_g_e(9 downto 8) & output_buf_g_e(1 DOWNTO 0));				
		thine_b_e_o <= (output_buf_b_e(7 downto 2) & output_buf_b_e(9 downto 8) & output_buf_b_e(1 DOWNTO 0));				
		thine_r_o_o <= (output_buf_r_o(7 downto 2) & output_buf_r_o(9 downto 8) & output_buf_r_o(1 DOWNTO 0));		
		thine_g_o_o <= (output_buf_g_o(7 downto 2) & output_buf_g_o(9 downto 8) & output_buf_g_o(1 DOWNTO 0));				
		thine_b_o_o <= (output_buf_b_o(7 downto 2) & output_buf_b_o(9 downto 8) & output_buf_b_o(1 DOWNTO 0));				
--		thine_r_e_o <= (output_buf_r_e(9 downto 2) & output_buf_r_e(1 DOWNTO 0));		
--		thine_g_e_o <= (output_buf_g_e(9 downto 2) & output_buf_g_e(1 DOWNTO 0));				
--		thine_b_e_o <= (output_buf_b_e(9 downto 2) & output_buf_b_e(1 DOWNTO 0));				
--		thine_r_o_o <= (output_buf_r_o(9 downto 2) & output_buf_r_o(1 DOWNTO 0));		
--		thine_g_o_o <= (output_buf_g_o(9 downto 2) & output_buf_g_o(1 DOWNTO 0));				
--		thine_b_o_o <= (output_buf_b_o(9 downto 2) & output_buf_b_o(1 DOWNTO 0));				
 

		thine_h	<= output_buf_hsync;
		thine_v	<= output_buf_vsync;
		thine_de <= output_buf_de;
		
		
--		buffer_in <= (corrected_r_e_i(9 downto 0)&input_buf_g_e(9 downto 0)&input_buf_b_e(9 downto 0)&input_buf_hsync&input_buf_de);
		buffer_in <= (input_buf_r_e(9 downto 0)&input_buf_g_e(9 downto 0)&input_buf_b_e(9 downto 0)&input_buf_hsync&input_buf_de);
		input_buf_r_e <= r_e_i;
		input_buf_g_e <= g_e_i;	
	 	input_buf_b_e <= b_e_i;
	 	input_buf_hsync <= hsync_in;
	 	input_buf_vsync <= vsync_in;
	 	input_buf_de <= de_in;
	 
		output_buf_r_e <= input_buf_r_e;
		output_buf_g_e <= input_buf_g_e;		
		output_buf_b_e <= input_buf_b_e;		
		output_buf_r_o <= input_buf_r_e;
		output_buf_g_o <= input_buf_g_e;		
		output_buf_b_o <= input_buf_b_e;		
		output_buf_hsync <= input_buf_hsync;
		output_buf_vsync <= input_buf_vsync;		
		output_buf_de <= input_buf_de;		

--		r_e_o <=output_buf_r_e;
--		r_o_o <=output_buf_r_o;		
--		g_e_o <=output_buf_g_e;
--		g_o_o <=output_buf_g_o;		
--		b_e_o <=output_buf_b_e;
--		b_o_o <=output_buf_b_o;		

		r_e_o <=(output_buf_r_e(7 downto 2) & output_buf_r_e(9 downto 8) & output_buf_r_e(1 DOWNTO 0));		
		r_o_o <=(output_buf_r_o(7 downto 2) & output_buf_r_o(9 downto 8) & output_buf_r_o(1 DOWNTO 0));		
		g_e_o <=(output_buf_g_e(7 downto 2) & output_buf_g_e(9 downto 8) & output_buf_g_e(1 DOWNTO 0));		
		g_o_o <=(output_buf_g_o(7 downto 2) & output_buf_g_o(9 downto 8) & output_buf_g_o(1 DOWNTO 0));		
		b_e_o <=(output_buf_b_e(7 downto 2) & output_buf_b_e(9 downto 8) & output_buf_b_e(1 DOWNTO 0));		
		b_o_o <=(output_buf_b_o(7 downto 2) & output_buf_b_o(9 downto 8) & output_buf_b_o(1 DOWNTO 0));		
		
		de_out<=output_buf_de;
		de_out_1 <= output_buf_de;
		hsync_out <= output_buf_hsync;
		hsync_out_1 <= output_buf_hsync;
		vsync_out <= output_buf_vsync;
		vsync_out_1 <= output_buf_vsync;


	END IF;
	
	end process;

	
end rtl;