cyclic5.vhd

来自「基于fpga的屏幕测试程序」· VHDL 代码 · 共 221 行

LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

--USE expander.inc
--USE fran_pg1.inc;

--LIBRARY altera_mf;
--USE altera_mf.altera_mf_components.all;

--Eric Funke, started 17th August 2004;
--Attempt to make Franpatg work in cyclic


--Yuning Zhang, alterring for the PDP measurement
--Start from 2005.03.21

-------------------------------------------------------------------
entity cyclic is 
port( 
	r_e_o			:	out std_logic_vector(9 downto 0);
	r_o_o			:	out std_logic_vector(9 downto 0);	
	g_e_o			:	out std_logic_vector(9 downto 0);
	g_o_o			:	out std_logic_vector(9 downto 0);	
	b_e_o			:	out std_logic_vector(9 downto 0);
	b_o_o			:	out std_logic_vector(9 downto 0);				
	de_out			:	out std_logic;
	hsync_out		:	out std_logic;
	vsync_out		:	out std_logic;			
	clk_out1		:	out std_logic;
	dclk			:	in  std_logic;
	clk1			:	in  std_logic;
	oei			    :	out std_logic;
	pd_out			:	out std_logic;
	pdwni			:	out std_logic;
	pixs_out		: 	out std_logic;
	h_countout		:	out std_logic;
	tp_in  		    :	in  std_logic_vector(10 downto 1);
	tp_out          :   out std_logic_vector(8 downto 1);
	edge_out		:	out std_logic;
	reset_in		:	in  std_logic;
	CPUGOo			:	out std_logic;
	PDPGOo			:	out std_logic;
	PDWNo			:	out std_logic;
	IRQ			    :	in  std_logic;
	scl_pld			:	inout std_logic;
	sda_pld			:	inout std_logic;
	parity_out_o	:	out std_logic;
	parity_out_e	:	out std_logic
);
 
end cyclic;

architecture rtl of cyclic is


	SIGNAL input_var	        :	std_logic;
	SIGNAL output_buf_r_e	    :	std_logic_vector(9 downto 0);
	SIGNAL output_buf_g_e	    :	std_logic_vector(9 downto 0);
	SIGNAL output_buf_b_e	    :	std_logic_vector(9 downto 0);
	SIGNAL output_buf_r_o	    :	std_logic_vector(9 downto 0);
	SIGNAL output_buf_g_o	    :	std_logic_vector(9 downto 0);
	SIGNAL output_buf_b_o	    :	std_logic_vector(9 downto 0);
	SIGNAL output_buf_hsync  	:	std_logic;
	SIGNAL output_buf_vsync  	:	std_logic;
	SIGNAL output_buf_de	    :	std_logic;
	SIGNAL expander_interface	:	std_logic_vector(7 downto 0);
	SIGNAL CPUGObuf,PDPGObuf,IRQbuf,PWDNbuf,PDWNObuf	:	std_logic;

	SIGNAL corrected_r_e_i		:	std_logic_vector(9 downto 0);
	SIGNAL thine_r_e_o			:	std_logic_vector(9 downto 0);	
	SIGNAL thine_g_e_o			:	std_logic_vector(9 downto 0);	
	SIGNAL thine_b_e_o			:	std_logic_vector(9 downto 0);		
	SIGNAL thine_r_o_o			:	std_logic_vector(9 downto 0);	
	SIGNAL thine_g_o_o			:	std_logic_vector(9 downto 0);	
	SIGNAL thine_b_o_o			:	std_logic_vector(9 downto 0);		
	SIGNAL thine_h,thine_v,thine_de		:	std_logic;
	SIGNAL old_de_in,h_count		:	std_logic;	
   	SIGNAL buffer_out_even,buffer_out_odd 	:	std_logic_vector(31 downto 0);
	SIGNAL buffer_in 			: 	std_logic_vector(31 downto 0);
	SIGNAL data_buf,data_buf2 		: 	std_logic_vector(31 downto 0);
--	SIGNAL field_ident_buf			:	std_logic;
    SIGNAL parity_buf               :   std_logic;
	SIGNAL old_vsync			:	std_logic;
	SIGNAL trigger_out      :   std_logic;
	SIGNAL Rpatgen			:	std_logic_vector(9 downto 0);
	SIGNAL Gpatgen			:	std_logic_vector(9 downto 0);
	SIGNAL Bpatgen			:	std_logic_vector(9 downto 0);


	component fran_pg 
	port(
		Red_out			    :	out std_logic_vector(9 downto 0);
		Green_out		    :	out std_logic_vector(9 downto 0);
		Blue_out	    	:	out std_logic_vector(9 downto 0);
		Xpander			    :	in std_logic_vector(7 downto 0);
		NBlank_out  		:	out std_logic;
		HSync_out	    	:	out std_logic;
		VSync_out		    :	out std_logic;	
	
		clk1			    :	in std_logic;

        IRQ 			    :	in std_logic; 
		CPUGO		    	:	out std_logic;
		PDPGO			    :	out std_logic;
		PWDN			    :	out std_logic;
		parity_out          :   out std_logic;
		trigger_out         :   out std_logic 
	);
	end component;



	component expander 
	port(
		SCL					:	in std_logic; 
		SDA					:	in std_logic;
		expander_data_out			:	out std_logic_vector(7 downto 0);
		clk1					:	in std_logic
		);
	end component;

	component rgb10to10 
	port(
		Rpdp			:	inout std_logic_vector(9 downto 0);
		Gpdp			:	inout std_logic_vector(9 downto 0);
		Bpdp			:	inout std_logic_vector(9 downto 0);
		Rlcd			:	inout std_logic_vector(9 downto 0);
		Glcd			:	inout std_logic_vector(9 downto 0);
		Blcd			:	inout std_logic_vector(9 downto 0)
		);
	end component;


begin

	i2c_expander		:	expander
	PORT MAP (
		SCL			=> scl_pld,
		SDA			=> sda_pld,	
		expander_data_out  	=> expander_interface,
		clk1			=> clk1
	
	);
 
--	rgb10bitsconverter	:	rgb10to10_dummy -- AvD, use this for LCD convention
	rgb10bitsconverter	:	rgb10to10       -- AvD, use this for PDP convention
	PORT MAP (
		Rpdp			=> Rpatgen,
		Gpdp			=> Gpatgen,
		Bpdp			=> Bpatgen,
		Rlcd			=> output_buf_r_e,
		Glcd			=> output_buf_g_e,
		Blcd			=> output_buf_b_e
	);

	pattern_generator	:	fran_pg
	PORT MAP (
		Red_out			=> Rpatgen,
		Green_out		=> Gpatgen,
		Blue_out		=> Bpatgen,
		Xpander			=> expander_interface,
		NBlank_out		=> output_buf_de,
		HSync_out 		=> output_buf_hsync,
		VSync_out		=> output_buf_vsync,
		clk1			=> clk1,
		CPUGO			=> CPUGObuf,
		PDPGO			=> PDPGObuf,
		IRQ 			=> IRQbuf,
		PWDN			=> PDWNObuf,
		Trigger_out     => trigger_out,
		parity_out		=> parity_buf		--?not present in Cyclic layout #1 !!
			);




	process(clk1)
	begin
  	IF Rising_edge(clk1) THEN
		r_e_o 			<= output_buf_r_e;  			
		g_e_o 			<= output_buf_g_e;  			
		b_e_o 			<= output_buf_b_e;  			
		r_o_o 			<= output_buf_r_e;  			
		g_o_o 			<= output_buf_g_e;  			
		b_o_o 			<= output_buf_b_e;  			
		hsync_out 		<= output_buf_hsync;
		vsync_out 		<= output_buf_vsync;
		de_out 			<= output_buf_de;
		CPUGOo 			<= CPUGObuf;
		PDPGOo 			<= PDPGObuf;
		PDWNo			<= PDWNObuf;
		IRQbuf 			<= IRQ;
		
	END IF;
	end process;



	process(clk1)
	begin
  	IF (Rising_edge(clk1)) THEN
 		oei		<='0'; 			--oei selects the LVDS input output enable: '1' for normal output, '0' for tri stated outputs
 		pd_out 		<='1';		--pd_out selects the DVI. '1' = normal operation '0' = power down 
  		pdwni 		<= '0';		--pdwni selects the LVDS input power down: '1' for normal output 	 		
 		pixs_out 	<='0';      --low level indicates 24 bits/clock for DVI, high = 48 bits/clock
		edge_out 	<= tp_in(1);
	 	input_var 	<= tp_in(1);			
	END IF;
	end process;

	parity_out_o <= parity_buf ;
	parity_out_e <= parity_buf ; 

	clk_out1 <=	clk1;
	
	tp_out(1)<=trigger_out;
		
	tp_out(4)<=parity_buf ;
end rtl;