📄 perception.tdf
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include "fran_pg.inc";
include "lpm_compare";
include "lpm_counter.inc";
include "lpm_add_sub.inc";
include "lpm_divide.inc";
include "lpm_ram_dp.inc";
SUBDESIGN perception
(
clk_sel[3..0] : INPUT;
clk : INPUT;
HAC[10..0] : INPUT;
VAC[10..0] : INPUT;
act_hcounter[10..0] : INPUT;
act_vcounter[10..0] : INPUT;
vout_pulse : INPUT;
moving_dist[10..0] : INPUT;
vposition[10..0] : INPUT;
velocity[5..0] : INPUT;
simu_r_in[9..0] : INPUT;
simu_g_in[9..0] : INPUT;
simu_b_in[9..0] : INPUT;
simu_wraddr[7..0] : INPUT;
simu_ram_wren : INPUT;
moving_en : OUTPUT;
barflag_en : OUTPUT;
backgnd_en : OUTPUT;
simudata_en : OUTPUT;
simu_r_out[9..0] : OUTPUT;
simu_g_out[9..0] : OUTPUT;
simu_b_out[9..0] : OUTPUT;
)
VARIABLE
simu_r_ram,
simu_g_ram,
simu_b_ram:
lpm_ram_dp WITH (
LPM_WIDTH = 10,
LPM_WIDTHAD = 8
);
add_moving:
lpm_add_sub WITH (
LPM_WIDTH = 11,
LPM_DIRECTION = "ADD",
ONE_INPUT_IS_CONSTANT = "NO",
LPM_PIPELINE = 0
);
sub_moving:
lpm_add_sub WITH (
LPM_WIDTH = 11,
LPM_DIRECTION = "SUB",
ONE_INPUT_IS_CONSTANT = "NO",
LPM_PIPELINE = 0
);
sub_moving_initial_12b
: lpm_add_sub WITH (
LPM_WIDTH = 12,
LPM_DIRECTION = "SUB",
ONE_INPUT_IS_CONSTANT = "YES",
LPM_PIPELINE = 0
);
add_compare,
sub_compare,
load1,
load2
: lpm_compare WITH (
LPM_WIDTH = 11,
ONE_INPUT_IS_CONSTANT = "NO",
LPM_REPRESENTATION = "UNSIGNED",
LPM_PIPELINE = 2
);
sta_add,
end_add
: lpm_add_sub WITH (
LPM_WIDTH = 12,
LPM_DIRECTION = "ADD",
ONE_INPUT_IS_CONSTANT = "NO",
LPM_PIPELINE = 0
);
sta_add_sub_12b,
end_add_sub_12b
: lpm_add_sub WITH (
LPM_WIDTH = 12,
LPM_DIRECTION = "SUB",
ONE_INPUT_IS_CONSTANT = "YES",
LPM_PIPELINE = 0
);
sta_add_compare,
end_add_compare
: lpm_compare WITH (
LPM_WIDTH = 12,
ONE_INPUT_IS_CONSTANT = "YES",
LPM_REPRESENTATION = "UNSIGNED",
LPM_PIPELINE = 0
);
sta_end_compare
: lpm_compare WITH (
LPM_WIDTH = 11,
ONE_INPUT_IS_CONSTANT = "NO",
LPM_REPRESENTATION = "UNSIGNED",
LPM_PIPELINE = 1
);
------------------------------------------------------------------------------------
vposition_shift_vac
: lpm_add_sub WITH (
LPM_WIDTH = 12,
LPM_DIRECTION = "ADD", --1-add,0-sub
ONE_INPUT_IS_CONSTANT = "YES",
LPM_PIPELINE = 0
);
vsta_add,
vend_add
: lpm_add_sub WITH (
LPM_WIDTH = 12,
LPM_DIRECTION = "ADD",
ONE_INPUT_IS_CONSTANT = "NO",
LPM_PIPELINE = 0
);
vsta_module,
vend_module
: lpm_divide WITH (
LPM_WIDTHN = 12,
LPM_WIDTHD = 12,
LPM_TYPE = "LPM_DIVIDE",
LPM_NREPRESENTATION = "UNSIGNED",
LPM_HINT = "LPM_REMAINDERPOSITIVE=TRUE",
LPM_DREPRESENTATION = "UNSIGNED",
LPM_PIPELINE = 0
);
vload1,
vload2
: lpm_compare WITH (
LPM_WIDTH = 11,
ONE_INPUT_IS_CONSTANT = "YES",
LPM_REPRESENTATION = "UNSIGNED",
LPM_PIPELINE = 2
);
v_sta_end_compare
: lpm_compare WITH (
LPM_WIDTH = 11,
ONE_INPUT_IS_CONSTANT = "NO",
LPM_REPRESENTATION = "UNSIGNED",
LPM_PIPELINE = 0
);
add_moving_buffer[10..0] : DFFE;
--sub_moving_buffer[10..0] : DFFE;
moving_buffer[10..0] : NODE;
sta_moving_buffer[10..0] : NODE;
end_moving_buffer[10..0] : NODE;
loadvsta[10..0] : NODE;
loadvend[10..0] : NODE;
--loadvsta_add[10..0] : NODE;
--loadvend_add[10..0] : NODE;
--loadvsta_sub[10..0] : NODE;
--loadvend_sub[10..0] : NODE;
barflag_enable : NODE;
moving_henable1 : NODE;
moving_henable2 : NODE;
moving_henable : NODE;
moving_ven_dffe : DFFE;
moving_venable : NODE;
simu_enable : NODE;
simu_rdaddr[10..0] : NODE;
simu_r_node_out[9..0] : NODE;
simu_g_node_out[9..0] : NODE;
simu_b_node_out[9..0] : NODE;
-----------------------------------------------------------------------------------
BEGIN
add_moving.dataa[] = add_moving_buffer[].q;
add_moving.datab[] = (0,0,0,0,0,0,velocity[4..0]);
add_compare.dataa[] = add_moving.result[] ;
add_compare.datab[] = HAC[] ;
add_compare.clock = clk ;
add_moving_buffer[].clk = clk;
add_moving_buffer[].ena = vout_pulse;
CASE add_compare.ageb IS
WHEN 0 => add_moving_buffer[].d = add_moving.result[];
WHEN 1 => add_moving_buffer[].d = add_moving.result[]-HAC[] ;
END CASE;
moving_buffer[] = add_moving_buffer[].q;
sta_add.dataa[] = (0,0,HAC[10..1])-50;
sta_add.datab[] = (0,moving_buffer[]);
end_add.dataa[] = (0,0,HAC[10..1])+50;
end_add.datab[] = (0,moving_buffer[]);
sta_add_sub_12b.dataa[] = sta_add.result[];
sta_add_sub_12b.datab[] = (0,HAC[]) ;
end_add_sub_12b.dataa[] = end_add.result[];
end_add_sub_12b.datab[] = (0,HAC[]) ;
sta_add_compare.dataa[] = sta_add.result[];
sta_add_compare.datab[] = (0,HAC[]);
CASE sta_add_compare.ageb IS
WHEN 1 => sta_moving_buffer[] = sta_add_sub_12b.result[10..0];
WHEN 0 => sta_moving_buffer[] = sta_add.result[10..0];
END CASE;
end_add_compare.dataa[] = end_add.result[];
end_add_compare.datab[] = (0,HAC[]);
CASE end_add_compare.ageb IS
WHEN 1 => end_moving_buffer[] = end_add_sub_12b.result[10..0];
WHEN 0 => end_moving_buffer[] = end_add.result[10..0];
END CASE;
sta_end_compare.dataa[] = sta_moving_buffer[];
sta_end_compare.datab[] = end_moving_buffer[];
sta_end_compare.clock =clk;
load1.dataa[] = act_hcounter[];
load1.datab[] = sta_moving_buffer[];
load1.clock = clk ;
load2.dataa[] = act_hcounter[];
load2.datab[] = end_moving_buffer[];
load2.clock = clk ;
CASE sta_end_compare.alb IS
WHEN 1 => moving_henable1 = load1.ageb AND load2.alb;
WHEN 0 => moving_henable1 = load1.ageb OR load2.alb;
END CASE;
IF act_hcounter[] <= (0,HAC[10..1])-(0,moving_dist[10..1])+5 AND
act_hcounter[] >= (0,HAC[10..1])+(0,moving_dist[10..1])-5
THEN moving_henable2 = VCC;
ELSE moving_henable2 = GND;
END IF;
moving_henable = moving_henable1 AND moving_henable2;
---------------------------------------------------------------------------------------
vposition_shift_vac.dataa[]=(0,VAC[]);
vposition_shift_vac.datab[]=(0,0,vposition[9..0]);
--vposition_shift_vac.add_sub=vposition[10]; --1 add,0 sub
vsta_add.dataa[]=(0,0,VAC[10..1])-50;
vsta_add.datab[]=vposition_shift_vac.result[];
vend_add.dataa[]=(0,0,VAC[10..1])+50;
vend_add.datab[]=vposition_shift_vac.result[];
--vsta_add.dataa[]=(0,vsta_table1.q[]);
--vend_add.dataa[]=(0,vend_table1.q[]);
vsta_module.numer[]=vsta_add.result[];
vsta_module.denom[]=(0,VAC[]);
vend_module.numer[]=vend_add.result[];
vend_module.denom[]=(0,VAC[]);
loadvsta[] = vsta_module.remain[10..0];
loadvend[] = vend_module.remain[10..0];
vload1.dataa[] = act_vcounter[];
vload1.datab[] = loadvsta[];
vload1.clock = clk;
vload2.dataa[] = act_vcounter[];
vload2.datab[] = loadvend[];
vload2.clock = clk;
v_sta_end_compare.dataa[]=loadvsta[];
v_sta_end_compare.datab[]=loadvend[];
CASE v_sta_end_compare.alb IS
WHEN 1 => moving_ven_dffe.d = vload1.ageb AND vload2.alb;
WHEN 0 => moving_ven_dffe.d = vload1.ageb OR vload2.alb;
END CASE;
moving_ven_dffe.clk = clk;
moving_venable = moving_ven_dffe.q;
moving_en = moving_henable AND moving_venable;
-------------------------------------------------------------------------------------
IF act_hcounter[] >= (0,HAC[10..1])-(0,moving_dist[10..1])-5 AND
act_hcounter[] <= (0,HAC[10..1])-(0,moving_dist[10..1])+5 OR
act_hcounter[] >= (0,HAC[10..1])+(0,moving_dist[10..1])-5 AND
act_hcounter[] <= (0,HAC[10..1])+(0,moving_dist[10..1])+5
THEN barflag_enable = VCC;
ELSE barflag_enable = GND;
END IF;
barflag_en = barflag_enable;
-----------------------------------------------------------------------------------
IF act_vcounter[] >= (0,VAC[10..1])-50 AND act_vcounter[] <= (0,VAC[10..1])+50 THEN
IF act_hcounter[] >= (0,HAC[10..1])-100 AND act_hcounter[] < (0,HAC[10..1])+100
THEN simu_enable = VCC;
simu_rdaddr[] = act_hcounter[]-(0,VAC[10..1])-100;
ELSE simu_enable = GND;
simu_rdaddr[] = 0;
END IF;
ELSE simu_enable = GND;
simu_rdaddr[] = 0;
END IF;
simu_r_ram.wren = simu_ram_wren;
simu_g_ram.wren = simu_ram_wren;
simu_b_ram.wren = simu_ram_wren;
simu_r_ram.wrclock = clk;
simu_g_ram.wrclock = clk;
simu_b_ram.wrclock = clk;
simu_r_ram.wrclken = VCC;
simu_g_ram.wrclken = VCC;
simu_b_ram.wrclken = VCC;
simu_r_ram.data[] = simu_r_in[9..0];
simu_g_ram.data[] = simu_g_in[9..0];
simu_b_ram.data[] = simu_b_in[9..0];
simu_r_ram.wraddress[] = simu_wraddr[7..0];
simu_g_ram.wraddress[] = simu_wraddr[7..0];
simu_b_ram.wraddress[] = simu_wraddr[7..0];
simu_r_ram.rdaddress[] = simu_rdaddr[7..0];
simu_g_ram.rdaddress[] = simu_rdaddr[7..0];
simu_b_ram.rdaddress[] = simu_rdaddr[7..0];
simu_r_ram.rdclock = clk;
simu_g_ram.rdclock = clk;
simu_b_ram.rdclock = clk;
simu_r_ram.rdclken = VCC;
simu_g_ram.rdclken = VCC;
simu_b_ram.rdclken = VCC;
simu_r_node_out[9..0] = simu_r_ram.q[9..0];
simu_g_node_out[9..0] = simu_g_ram.q[9..0];
simu_b_node_out[9..0] = simu_b_ram.q[9..0];
simu_r_out[9..0] = simu_r_node_out[9..0];
simu_g_out[9..0] = simu_g_node_out[9..0];
simu_b_out[9..0] = simu_b_node_out[9..0];
simudata_en = simu_enable;
-------------------------------------------------------------------------------------
backgnd_en = NOT moving_en AND NOT barflag_en AND NOT simudata_en;
END;
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