frantic_42wvga_sdi_1_org.tdf

基于fpga的屏幕测试程序

vpos3.dataa[10..0] = act_vcounter.q[10..0];
vpos3.datab[10..0] = 398;
vpos3.clock = klok;

vpos5.dataa[10..0] = act_vcounter.q[10..0];
vpos5.datab[10..0] = 114;
vpos5.clock = klok;

vpos6.dataa[10..0] = act_vcounter.q[10..0];
vpos6.datab[10..0] = 284;
vpos6.clock = klok;

vpos7.dataa[10..0] = act_vcounter.q[10..0];
vpos7.datab[10..0] = 455;
vpos7.clock = klok;

vcentblock1.dataa[10..0] = act_vcounter.q[10..0];
vcentblock1.datab[10..0] = 215;
vcentblock1.clock = klok;

vcentblock2.dataa[10..0] = act_vcounter.q[10..0];
vcentblock2.datab[10..0] = 255;
vcentblock2.clock = klok;

hcentblock1.dataa[10..0] = act_counter.q[10..0];
hcentblock1.datab[10..0] = 400;
hcentblock1.clock = klok;

hcentblock2.dataa[10..0] = act_counter.q[10..0];
hcentblock2.datab[10..0] = 450;
hcentblock2.clock = klok;

ramp1.clk = klok;
ramp1.S   = start_ramp1.aeb;
    ramp1.R	  = start_ramp2.aeb;

ramp2.clk = klok;
ramp2.S   = start_ramp2.aeb;
    ramp2.R	  = start_ramp3.aeb;

ramp3.clk = klok;
ramp3.S   = start_ramp3.aeb;
    ramp3.R	  = start_ramp4.aeb;

ramp4.clk = klok;
ramp4.S   = start_ramp4.aeb;
    ramp4.R	  = start_ramp1.aeb;


hcentblock.clk = klok;
hcentblock.S   = (hcentblock1.aeb);
hcentblock.R   = (hcentblock2.aeb);

vcentblock.clk = klok;
vcentblock.S   = (vcentblock1.aeb);
vcentblock.R   = (vcentblock2.aeb);

vvid_act_blocks.clk = klok;
vvid_act_blocks.S   = (vpos1.aeb OR vpos2.aeb OR vpos3.aeb );
vvid_act_blocks.R   = (vpos5.aeb OR vpos6.aeb OR vpos7.aeb );

hvid_act_blocks.clk = klok;
hvid_act_blocks.S   = (hpos1.aeb OR hpos2.aeb OR hpos3.aeb );
hvid_act_blocks.R   = (hpos5.aeb OR hpos6.aeb OR hpos7.aeb );



--AeB = lpm_compare_component.AeB;
start_h.dataa[10..0] = h_counter.q[10..0];
start_h.datab[10..0] = 1032;						--#pixels hperiod minus 3
start_h.clock = klok;

start_h_delay[0].clk = klok;
start_h_delay[0].d = start_h.aeb;

start_h_delay[1].clk = klok;
start_h_delay[1].d = start_h_delay[0].q;


--AeB = lpm_compare_component.AeB;
end_h.dataa[10..0] = h_counter.q[10..0];
end_h.datab[10..0] = 16;
end_h.clock = klok;


--AeB = lpm_compare_component.AeB;
start_n.dataa[10..0] = h_counter.q[10..0];
start_n.datab[10..0] = 39;
start_n.clock = klok;

--AeB = lpm_compare_component.AeB;
end_n.dataa[10..0] = h_counter.q[10..0];
end_n.datab[10..0] = 891;
end_n.clock = klok;

--AeB = lpm_compare_component.AeB;
start_v.dataa[10..0] = v_counter.q[10..0];
start_v.datab[10..0] = V_sync_end_count[10..0].q;
start_v.clock = klok;

start_v_delay.d = start_v.aeb;
start_v_delay.clk = klok;

start_v_pulse = (start_v.aeb AND NOT(start_v_delay.q));

start_v_pulse_delay.clk =klok;
start_v_pulse_delay.d =start_v_pulse;

--AeB = lpm_compare_component.AeB;
end_v.dataa[10..0] = v_counter.q[10..0];
end_v.datab[10..0] = 1;
end_v.clock = klok;

--AeB = lpm_compare_component.AeB;
start_vn.dataa[10..0] = v_counter.q[10..0];
start_vn.datab[10..0] = 13;						
start_vn.clock = klok;
--AeB = lpm_compare_component.AeB;
end_vn.dataa[10..0] = v_counter.q[10..0];
end_vn.datab[10..0] = 493;
end_vn.clock = klok;

----------------------------------------------------------------------------------
--Moveramp section
----------------------------------------------------------------------------------
    moverampwa.address[9..0] 	= ramp_counter.q[9..0];
	moverampwa.inclock 			= klok;
	moverampwa.outclock			= klok;

    moverampwb.address[9..0] 	= ramp_counter.q[9..0];
	moverampwb.inclock 			= klok;
	moverampwb.outclock			= klok;

--    moverampra.address[9..0] 	= ramp_counter.q[9..0];
--	moverampra.inclock 			= klok;
--	moverampra.outclock			= klok;

--    moveramprb.address[9..0] 	= ramp_counter.q[9..0];
--	moveramprb.inclock 			= klok;
--	moveramprb.outclock			= klok;

    moverampga.address[9..0] 	= ramp_counter.q[9..0];
	moverampga.inclock 			= klok;
	moverampga.outclock			= klok;

    moverampgb.address[9..0] 	= ramp_counter.q[9..0];
	moverampgb.inclock 			= klok;
	moverampgb.outclock			= klok;

--    moverampba.address[9..0] 	= ramp_counter.q[9..0];
--	moverampba.inclock 			= klok;
--	moverampba.outclock			= klok;

--    moverampbb.address[9..0] 	= ramp_counter.q[9..0];
--	moverampbb.inclock 			= klok;
--	moverampbb.outclock			= klok;



	-- = lpm_counter_component.q[9..0];
	ramp_counter.sload = start_h.aeb;
	ramp_counter.clock = klok;
	ramp_counter.data[9..0] = start_point_buffer[9..0].q;
	ramp_counter.sclr = ramp_counter_compare.aeb AND NOT (start_h.aeb);


	CASE fullregbuf[5..4].q IS
	WHEN 0 =>
		start_point.dataa[9..0] = 0;
	WHEN 1 =>
		start_point.dataa[9..0] = 5;
	WHEN 2 =>
		start_point.dataa[9..0] = 6;
	WHEN 3 =>
		start_point.dataa[9..0] = 10;
	END CASE;

	start_point.datab[9..0] = start_point_buffer[9..0].q;
    IF NOT(start_pointer_compare.ageb)
	THEN
	    start_point_buffer[9..0].d = start_point.result[9..0];
	ELSE
	    start_point_buffer[9..0].d = GND;
	END IF;
    start_point_buffer[].clk = klok;
	start_point_buffer[].ena = vout_pulse;--start_v.aeb;

	ramp_counter_compare.dataa[9..0] = ramp_counter.q[9..0];
	ramp_counter_compare.datab[9..0] = 849;
	ramp_counter_compare.clock = klok;

	start_pointer_compare.dataa[9..0] = start_point_buffer[9..0].q;
	start_pointer_compare.datab[9..0] = 846;


    CASE (act_vcounter.q[8..6]) IS
	WHEN 0 =>
	  move_rampr[9..2].d = moverampwa.q[7..0];	  	  
	  move_rampg[9..2].d = moverampwa.q[7..0];	  	  
	  move_rampb[9..2].d = moverampwa.q[7..0];	  	  
	  move_rampr[1..0].d = GND;	  	  
	  move_rampg[1..0].d = GND;	  	  
	  move_rampb[1..0].d = GND;	  	  
	WHEN 1 =>
	  move_rampr[9..2].d = moverampwb.q[7..0];	  	  
	  move_rampg[9..2].d = moverampwb.q[7..0];	  	  
	  move_rampb[9..2].d = moverampwb.q[7..0];	  	  
	  move_rampr[1..0].d = GND;	  	  
	  move_rampg[1..0].d = GND;	  	  
	  move_rampb[1..0].d = GND;	  	  
	WHEN 2 =>
	  move_rampr[9..2].d = moverampwb.q[7..0];	  	  
	  move_rampg[9..2].d = moverampgb.q[7..0];	  	  
	  move_rampb[9..2].d = GND;	  	  
	  move_rampr[1..0].d = GND;	  	  
	  move_rampg[1..0].d = GND;	  	  
	  move_rampb[1..0].d = GND;	  	  
	WHEN 3 =>
	  move_rampr[9..2].d = moverampwa.q[7..0];	  	  
	  move_rampg[9..2].d = moverampga.q[7..0];	  	  
	  move_rampb[9..2].d = GND;	  	  
	  move_rampr[1..0].d = GND;	  	  
	  move_rampg[1..0].d = GND;	  	  
	  move_rampb[1..0].d = GND;	  	  
	WHEN 4 =>
	  move_rampr[9..2].d = moverampwa.q[7..0];	  	  
	  move_rampg[9..2].d = moverampwa.q[7..0];	  	  
	  move_rampb[9..2].d = moverampwa.q[7..0];	  	  
	  move_rampr[1..0].d = GND;	  	  
	  move_rampg[1..0].d = GND;	  	  
	  move_rampb[1..0].d = GND;	  	  
	WHEN 5 =>
	  move_rampr[9..2].d = moverampwb.q[7..0];	  	  
	  move_rampg[9..2].d = moverampwb.q[7..0];	  	  
	  move_rampb[9..2].d = moverampwb.q[7..0];	  	  
	  move_rampr[1..0].d = GND;	  	  
	  move_rampg[1..0].d = GND;	  	  
	  move_rampb[1..0].d = GND;	  	  
%	WHEN 6 =>
	  move_rampr[9..0].d = moverampba.q[9..0];	  	  
	  move_rampg[9..0].d = moverampba.q[9..0];	  	  
	  move_rampb[9..0].d = moverampba.q[9..0];	  	  
	WHEN 7 =>
	  move_rampr[9..0].d = moverampbb.q[9..0];	  	  
	  move_rampg[9..0].d = moverampbb.q[9..0];	  	  
	  move_rampb[9..0].d = moverampbb.q[9..0];	  	  %
	WHEN OTHERS =>
	  move_rampr[].d = GND;
	  move_rampg[].d = GND;
	  move_rampb[].d = GND;
	END CASE;

move_rampr[].clk = klok;
move_rampg[].clk = klok;
move_rampb[].clk = klok;

----------------------------------------------------------------------------
	vload1.dataa[10..0] = act_vcounter.q[10..0];
	vload1.datab[10..0] = loadvstart[10..0];
	vload1.clock = klok;

	vload2.dataa[10..0] = act_vcounter.q[10..0];
	vload2.datab[10..0] = loadvend[10..0];
	vload2.clock = klok;

	hload1.dataa[10..0] = act_counter.q[10..0];
	hload1.datab[10..0] = loadhstart[10..0];
	hload1.clock = klok;

	hload2.dataa[10..0] = act_counter.q[10..0];
	hload2.datab[10..0] = loadhend[10..0];
	hload2.clock = klok;

	hloadblock.clk = klok;
	hloadblock.S   = (hload1.aeb);
	hloadblock.R   = (hload2.aeb);

	vloadblock.clk = klok;
	vloadblock.S   = (vload1.aeb);
	vloadblock.R   = (vload2.aeb);
----------------------------------------------------------------------------

hsync_art.clk = klok;
hsync_art.R = start_h.aeb;
hsync_art.S = end_h.aeb;

vsync_art.clk = klok;
--vsync_art.r = ((start_v.aeb)  AND (h_counter.q[] == 600));
--vsync_art.s = ((end_v.aeb) AND (h_counter.q[] == 600));
vsync_art.r = (start_v.aeb);
vsync_art.s = (end_v.aeb );


vout_delay.d = vsync_art.q;
vout_delay.clk = klok;

vout_pulse = ((vsync_art.q) AND NOT(vout_delay.q));

nblankv_art.clk = klok;
nblankv_art.s = start_vn.aeb;
nblankv_art.r = end_vn.aeb OR start_v.aeb;

nblankv_art_delay.d = nblankv_art.q;
nblankv_art_delay.clk = klok;

start_nv_pulse = (nblankv_art.q AND NOT(nblankv_art_delay.q));

nblank_art.clk = klok;
nblank_art.s = start_n.aeb and nblankv_art.q;
nblank_art.r = end_n.aeb;


nblank_art_delay[].clk = klok;
nblank_art_delay1.d = NBLANK_art.q;
nblank_art_delay2.d = nblank_art_delay1.q;
nblank_art_delay3.d = nblank_art_delay2.q;
nblank_art_delay4.d = nblank_art_delay3.q;

Nblank_display		=	NBLANK_art_delay4.q;


Hsync_display		=	hsync_art.q;
Vsync_display		=	vsync_art.q;


--test3 = Hsync_display;
--test4 = Vsync_display;
--test5 = Nblank_display;
--test6 = Field_ident;

----------------------------------------------------------------------------------
--PDP control section
----------------------------------------------------------------------------------
--SCLO 	= 	SCL_in;
--SDAO 	= 	SDA_in;
--IRQ = ;
CPUGO 	= 	fullregbuf[28];
PDPGO 	= 	fullregbuf[29];
PWDN	=	fullregbuf[30];



----------------------------------------------------------------------------------
--Parity section
----------------------------------------------------------------------------------
--fullregbuf[27..26]  0:parity=gnd  1:parity=VCC 2:parity=parity_art 3:parity=not(parity_art)

CASE fullregbuf[27..26] IS
WHEN 0 =>
  Field_ident = GND;
WHEN 1 =>
  Field_ident = VCC;
WHEN 2 =>
  Field_ident = par_art;
WHEN 3 =>
  Field_ident = NOT(par_art);
END CASE;

par_jk.J = VCC;
par_jk.K = VCC;
par_jk.clk = Vsync_display;
par_art = par_jk.q;

--Field_ident = par_art;
Enable_display = VCC;
HQ_enable			= fullregbuf[25].q;
HiBrite				= fullregbuf[6].q;

IF fullregbuf[31]
THEN
  RedValue[9..2]		= cyclevalue.q[7..0];
  GreenValue[9..2]		= cyclevalue.q[7..0];
  BlueValue[9..2]		= cyclevalue.q[7..0];
  RedValue[1..0]		= GND;
  GreenValue[1..0]		= GND;
  BlueValue[1..0]		= GND;
ELSE
  RedValue[9..2]		= fullregbuf[21..14].q;
  GreenValue[9..2]		= fullregbuf[21..14].q;
  BlueValue[9..2]		= fullregbuf[21..14].q;
  RedValue[1..0]		= GND;
  GreenValue[1..0]		= GND;
  BlueValue[1..0]		= GND;
END IF;

cyclevalue.clock = klok;
cyclevalue.clk_en = Vout_pulse;
cyclevalue.updown = updown.q;


cyclevalue_compare_low.clock = klok;
cyclevalue_compare_low.dataa[7..0] = cyclevalue.q[7..0];
cyclevalue_compare_low.datab[7..0] = 3;

cyclevalue_compare_high.clock = klok;
cyclevalue_compare_high.dataa[7..0] = cyclevalue.q[7..0];
cyclevalue_compare_high.datab[7..0] = 252;

updown.S = cyclevalue_compare_low.aeb;
updown.R = cyclevalue_compare_high.aeb;
updown.clk = klok;


Renab				= fullregbuf[22];
Genab				= fullregbuf[23];
Benab				= fullregbuf[24];


----------------------------------------------------------------------------------
--sync jump section
----------------------------------------------------------------------------------
%
IF fullregbuf[13].q THEN
	V_sync_temp_count[10..0] = 533;  --60Hz  --field time in #lines
ELSE
	V_sync_temp_count[10..0] = 639;  --50Hz
END IF;
%

vsync_adder.dataa = 8;
vsync_adder.datab[10..10] = GND; 
vsync_adder.datab[9..3] = fullregbuf[38..32];
vsync_adder.datab[2..2] = fullregbuf[48..48];
vsync_adder.datab[1..0] = GND;

IF fullregbuf[47].q THEN
	V_sync_temp_count = vsync_adder.result; 
ELSE
	IF fullregbuf[13].q THEN
		V_sync_temp_count[10..0] = 533;  --60Hz  --field time in #lines
	ELSE
		V_sync_temp_count[10..0] = 639;  --50Hz
	END IF;
END IF;

old_sync_jump.d = fullregbuf[46].q;		--a low-to-high transition should produce a sync jump
old_sync_jump.ena = start_v_pulse;
old_sync_jump.clk = klok;

command_to_jump.d = NOT(old_sync_jump) AND fullregbuf[46].q;
command_to_jump.clk = klok;
command_to_jump.ena = start_v_pulse;

IF fullregbuf[46].q THEN					
	video_mode[4..0] = 5; --normal mode
ELSE
	video_mode[4..0] = ((NOT(fullregbuf[7].q)),fullregbuf[3..0].q); --normal mode
END IF;


IF command_to_jump.q THEN					
	V_sync_end_count[10..0].d = (fullregbuf[45..39].q,1,1,1,1);  --sync jump mode
ELSE
	V_sync_end_count[10..0].d = V_sync_temp_count[10..0];  --normal mode
END IF;

V_sync_end_count[10..0].clk = klok;
V_sync_end_count[10..0].ena = start_v_pulse_delay;

END;