📄 frantic_42wvga_sdi_1_org.tdf
字号:
TITLE " plasma interface panel for development";
%added a sync jump function for FTV2.3, ripped TMF pattern%
%adapted spec to 9 blocks to accomodate new FHP testspec%
%AvD, NO LONGER, This is a testpattern generator for the Frantic board, intended for 32inch ALiS PDP%
%This is a testpattern generator for the Frantic board, intended for SDI 42" WVGA PDP (852H*480V)%
%The parameters of the pattern are in a V-synchronised buffer "fullregbuf[48..0]",
filled by one 8-bits expander, which receives the following format:
first byte
7 6 5 4 3 2 1 0
1 [ "address" ]
second byte
7 6 5 4 3 2 1 0
0 [ "data" ]
"address" can be currently 0..naddress-1, and for each address the 7 bits "data" is put
in a part of the naddress*7 bits fullregbuf.
(currently naddress = 7)
fullregbuf[3..0] pattern mode
0 RGB ramps
1 9 blocks
2 full screen
3 centre block
4 black
5 variable load block
6 moving ramps
7 full screen grey scale
8 crosshatch
9 TMF
10 colourbar 8 bars
11 worst case addressing current
fullregbuf[5..4] ramp speed
0 0 pixels/frame
1 5 pixels/frame
2 6 pixels/frame
3 10 pixels/frame
fullregbuf[6] HiBrite
0 off
1 on
fullregbuf[7] picture enabled
0 Black indeed
1 non-black possible
fullregbuf[12..8] size loadblock
0 variable load 0.5 percent
1 variable load 1 percent
2 variable load 2
3 variable load 3
4 variable load 4
5 variable load 5
6 variable load 6
7 variable load 7
8 variable load 8
9 variable load 9
10 variable load 10
11 variable load 12
12 variable load 14
13 variable load 16
14 variable load 18
15 variable load 20
16 variable load 25
17 variable load 30
18 variable load 35
19 variable load 40
20 variable load 45
21 variable load 50
22 variable load 55
23 variable load 60
24 variable load 65
25 variable load 70
26 variable load 75
27 variable load 80
28 variable load 85
29 variable load 90
30 variable load 95
31 variable load 100 percent
fullregbuf[13] fV
0 50Hz
1 60Hz
fullregbuf[21..14] value of "variable load white"
0 0
1 1
...
255 255
fullregbuf[22] Red enable of "variable load white"
fullregbuf[23] Green enable of "variable load white"
fullregbuf[24] Blue enable of "variable load white"
fullregbuf[25] HQ_enable
fullregbuf[27..26] 0:parity=gnd 1:parity=VCC 2:parity=parity_art 3:parity=not(parity_art)
fullregbuf[28] CPUGO
fullregbuf[29] PDPGO
fullregbuf[30] PWDN
fullregbuf[31] Cycle grey
fullregbuf[38..32] most significant part of programmable vperiod
fullregbuf[45..39] field time for sync jump
fullregbuf[46] sync command
fullregbuf[47] programmable vperiod (0: 50Hz/60Hz 1: programmable)
fullregbuf[48] least significant part of programmable vperiod
%
%============================================================================================%
include "lpm_counter.inc";
include "lpm_compare.inc";
include "lpm_rom.inc";
include "importN7bits.inc";
include "lpm_add_sub.inc";
SUBDESIGN frantic_42WVGA_SDI_1
(
clock : INPUT;
--freerun_clock : INPUT;
Red0 : INPUT;
Red1 : INPUT;
Red2 : INPUT;
Red3 : INPUT;
Red4 : INPUT;
Red5 : INPUT;
Red6 : INPUT;
Red7 : INPUT;
Red8 : INPUT;
Red9 : INPUT;
Green0 : INPUT;
Green1 : INPUT;
Green2 : INPUT;
Green3 : INPUT;
Green4 : INPUT;
Green5 : INPUT;
Green6 : INPUT;
Green7 : INPUT;
Green8 : INPUT;
Green9 : INPUT;
Blue0 : INPUT;
Blue1 : INPUT;
Blue2 : INPUT;
Blue3 : INPUT;
Blue4 : INPUT;
Blue5 : INPUT;
Blue6 : INPUT;
Blue7 : INPUT;
Blue8 : INPUT;
Blue9 : INPUT;
Hsync : INPUT;
Vsync : INPUT;
NBLANKin : INPUT;
Xpander0 : INPUT;
Xpander1 : INPUT;
Xpander2 : INPUT;
Xpander3 : INPUT;
Xpander4 : INPUT;
Xpander5 : INPUT;
Xpander6 : INPUT;
Xpander7 : INPUT;
SDA_in : INPUT;
SCL_in : INPUT;
parity_in : INPUT;
DISPEN : INPUT;
HQ_en : INPUT;
Red_out0 : OUTPUT;
Red_out1 : OUTPUT;
Red_out2 : OUTPUT;
Red_out3 : OUTPUT;
Red_out4 : OUTPUT;
Red_out5 : OUTPUT;
Red_out6 : OUTPUT;
Red_out7 : OUTPUT;
Red_out8 : OUTPUT;
Red_out9 : OUTPUT;
Green_out0 : OUTPUT;
Green_out1 : OUTPUT;
Green_out2 : OUTPUT;
Green_out3 : OUTPUT;
Green_out4 : OUTPUT;
Green_out5 : OUTPUT;
Green_out6 : OUTPUT;
Green_out7 : OUTPUT;
Green_out8 : OUTPUT;
Green_out9 : OUTPUT;
Blue_out0 : OUTPUT;
Blue_out1 : OUTPUT;
Blue_out2 : OUTPUT;
Blue_out3 : OUTPUT;
Blue_out4 : OUTPUT;
Blue_out5 : OUTPUT;
Blue_out6 : OUTPUT;
Blue_out7 : OUTPUT;
Blue_out8 : OUTPUT;
Blue_out9 : OUTPUT;
Hsync_display : OUTPUT;
Vsync_display : OUTPUT;
Nblank_display : OUTPUT;
enable_display : OUTPUT;
Field_ident : OUTPUT;
HQ_enable : OUTPUT;
HiBrite : OUTPUT;
--outtest[9..0] : OUTPUT;
--dummy_freerun_clock : OUTPUT;
--dummy_out : OUTPUT;
SDA_out : OUTPUT;
SCLO : INPUT;
SDAO : INPUT;
CPUGO : OUTPUT;
PDPGO : OUTPUT;
IRQ : INPUT;
PWDN : OUTPUT;
test[9..7] : OUTPUT;
test5 : OUTPUT;
test4 : OUTPUT;
test3 : OUTPUT;
dumscl,dumsda : INPUT;
)
VARIABLE
tristate[5..3] : TRI; --these three output pins need to be kept in high-z !
dummyz[5..3] : NODE;
loadhstart[10..0] : NODE;
loadvstart[10..0] : NODE;
loadhend[10..0] : NODE;
loadvend[10..0] : NODE;
Red_in[9..0] : DFF;
Green_in[9..0] : DFF;
Blue_in[9..0] : DFF;
HSYNC_buf : DFF;
VSYNC_buf : DFF;
NBLANKin_buf : DFF;
hsync_art : SRFF;
vsync_art : SRFF;
vout_delay : DFF;
vout_pulse : NODE;
nblankv_art : SRFF;
nblank_art : SRFF;
nblank_art_delay[1..4] : DFF;
par_art : NODE;
par_jk : JKFF;
vvid_act_blocks : SRFF;
hvid_act_blocks : SRFF;
hcentblock : SRFF;
vcentblock : SRFF;
hloadblock,vloadblock : SRFF;
ramp1 : SRFF;
ramp2 : SRFF;
ramp3 : SRFF;
ramp4 : SRFF;
move_rampr[9..0] : DFF;
move_rampg[9..0] : DFF;
move_rampb[9..0] : DFF;
start_point_buffer[9..0] : DFFE;
--input section
Red_art[9..0] : DFF;
Green_art[9..0] : DFF;
Blue_art[9..0] : DFF;
fullregbuf[48..0] : DFFE;
fullreg : importN7bits;
cross : DFF;
tri_stateSDA : DFF;
tri_stateSCL : DFF;
start_h_delay[1..0] : DFF;
start_v_delay : DFF;
start_v_pulse : NODE;
start_v_pulse_delay : DFF;
nblankv_art_delay : DFF;
updown : SRFF;
colourbar_r : DFF;
colourbar_g : DFF;
colourbar_b : DFF;
adressingR : DFF;
adressingG : DFF;
adressingB : DFF;
adres_mode_active : DFF;
adres_mode_active_delay : DFF;
adres_mode_active_pulse : DFF;
allow_adres_pattern : SRFF;
set_subpix : DFF;
start_nv_pulse : NODE;
start_h_pulse : NODE;
RedValue[9..0] : NODE;
GreenValue[9..0] : NODE;
BlueValue[9..0] : NODE;
Renab : NODE;
Genab : NODE;
Benab : NODE;
klok : NODE;
old_sync_jump : DFFE;
V_sync_end_count[10..0] : DFFE;
V_sync_temp_count[10..0] : NODE;
command_to_jump : DFFE;
video_mode[4..0] : NODE;
rampje : LPM_ROM WITH (
LPM_WIDTH = 8,
LPM_WIDTHAD = 10,
LPM_ADDRESS_CONTROL = "REGISTERED",
LPM_OUTDATA = "REGISTERED",
LPM_FILE = "linramp.mif"
);
moverampwa : LPM_ROM WITH (
LPM_WIDTH = 8,
LPM_WIDTHAD = 10,
LPM_ADDRESS_CONTROL = "REGISTERED",
LPM_OUTDATA = "REGISTERED",
LPM_FILE = "moverampwa.mif"
);
moverampwb : LPM_ROM WITH (
LPM_WIDTH = 8,
LPM_WIDTHAD = 10,
LPM_ADDRESS_CONTROL = "REGISTERED",
LPM_OUTDATA = "REGISTERED",
LPM_FILE = "moverampwb.mif"
);
%moverampra : LPM_ROM WITH (
LPM_WIDTH = 8,
LPM_WIDTHAD = 10,
LPM_ADDRESS_CONTROL = "REGISTERED",
LPM_OUTDATA = "REGISTERED",
LPM_FILE = "moverampra.mif"
);%
%moveramprb : LPM_ROM WITH (
LPM_WIDTH = 8,
LPM_WIDTHAD = 10,
LPM_ADDRESS_CONTROL = "REGISTERED",
LPM_OUTDATA = "REGISTERED",
LPM_FILE = "moveramprb.mif"
);%
moverampga : LPM_ROM WITH (
LPM_WIDTH = 8,
LPM_WIDTHAD = 10,
LPM_ADDRESS_CONTROL = "REGISTERED",
LPM_OUTDATA = "REGISTERED",
LPM_FILE = "moverampga.mif"
);
moverampgb : LPM_ROM WITH (
LPM_WIDTH = 8,
LPM_WIDTHAD = 10,
LPM_ADDRESS_CONTROL = "REGISTERED",
LPM_OUTDATA = "REGISTERED",
LPM_FILE = "moverampgb.mif"
);
%moverampba : LPM_ROM WITH (
LPM_WIDTH = 8,
LPM_WIDTHAD = 10,
LPM_ADDRESS_CONTROL = "REGISTERED",
LPM_OUTDATA = "REGISTERED",
LPM_FILE = "moverampba.mif"
);%
%moverampbb : LPM_ROM WITH (
LPM_WIDTH = 8,
LPM_WIDTHAD = 10,
LPM_ADDRESS_CONTROL = "REGISTERED",
LPM_OUTDATA = "REGISTERED",
LPM_FILE = "moverampbb.mif"
);
%
ramp_counter : lpm_counter WITH (
LPM_WIDTH = 10,
LPM_DIRECTION = "UP"
);
ramp_counter_compare : lpm_compare WITH (
LPM_WIDTH = 10,
ONE_INPUT_IS_CONSTANT = "YES",
LPM_REPRESENTATION = "UNSIGNED",
LPM_PIPELINE = 2
);
start_pointer_compare : lpm_compare WITH (
LPM_WIDTH = 10,
ONE_INPUT_IS_CONSTANT = "YES",
LPM_REPRESENTATION = "UNSIGNED",
LPM_PIPELINE = 0
);
start_point : lpm_add_sub WITH (
LPM_WIDTH = 10,
LPM_DIRECTION = "ADD",
ONE_INPUT_IS_CONSTANT = "NO",
LPM_PIPELINE = 0
);
vload1 : lpm_compare WITH (
LPM_WIDTH = 11,
ONE_INPUT_IS_CONSTANT = "YES",
LPM_REPRESENTATION = "UNSIGNED",
LPM_PIPELINE = 2
);
vload2 : lpm_compare WITH (
LPM_WIDTH = 11,
ONE_INPUT_IS_CONSTANT = "YES",
LPM_REPRESENTATION = "UNSIGNED",
LPM_PIPELINE = 2
);
hload1 : lpm_compare WITH (
LPM_WIDTH = 11,
ONE_INPUT_IS_CONSTANT = "YES",
LPM_REPRESENTATION = "UNSIGNED",
LPM_PIPELINE = 2
);
hload2 : lpm_compare WITH (
LPM_WIDTH = 11,
ONE_INPUT_IS_CONSTANT = "YES",
LPM_REPRESENTATION = "UNSIGNED",
LPM_PIPELINE = 2
);
start_ramp1 : lpm_compare WITH (
LPM_WIDTH = 11,
ONE_INPUT_IS_CONSTANT = "YES",
LPM_REPRESENTATION = "UNSIGNED",
LPM_PIPELINE = 2
);
start_ramp2 : lpm_compare WITH (
LPM_WIDTH = 11,
ONE_INPUT_IS_CONSTANT = "YES",
LPM_REPRESENTATION = "UNSIGNED",
LPM_PIPELINE = 2
);
start_ramp3 : lpm_compare WITH (
LPM_WIDTH = 11,
ONE_INPUT_IS_CONSTANT = "YES",
LPM_REPRESENTATION = "UNSIGNED",
LPM_PIPELINE = 2
);
start_ramp4 : lpm_compare WITH (
LPM_WIDTH = 11,
ONE_INPUT_IS_CONSTANT = "YES",
LPM_REPRESENTATION = "UNSIGNED",
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -