experiment.vhd

可以受上位机控制的通过fpga的视频信号发生器程序

LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY experiment IS PORT
( clk    : IN std_logic;
  vcount : IN std_logic_vector(11 DOWNTO 0);
  hcount : IN std_logic_vector(10 DOWNTO 0);
  clken_fcount: IN std_logic;
  pattern: IN std_logic_vector(3  DOWNTO 0);
  distance:IN std_logic_vector(3  DOWNTO 0);
  distance1      : IN  std_logic_vector(3 DOWNTO 0);
  level1   : IN  std_logic_vector(7 DOWNTO 0);
  level2      : IN  std_logic_vector(7 DOWNTO 0);
   level3      : IN  std_logic_vector(7 DOWNTO 0);
   selection:IN std_logic_vector(1  DOWNTO 0);
  out_r_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_g_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_b_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_r_o   : OUT std_logic_vector(7 DOWNTO 0);
  out_g_o   : OUT std_logic_vector(7 DOWNTO 0);
  out_b_o   : OUT std_logic_vector(7 DOWNTO 0)
);
CONSTANT HAC:integer:=640;   -- horizontal active pixels 1448*1151
CONSTANT HSY:integer:=20;     -- horizontal sync width (negative polarity)
CONSTANT HBP:integer:=20;     -- horizontal back porch
CONSTANT VAC:integer:=1024;    -- vertical active pixels
CONSTANT VSY:integer:=25;      -- vertical sync width (negative polarity)
CONSTANT VBP:integer:=25;     -- vertical back porch
END experiment;
ARCHITECTURE rtl OF experiment IS

SIGNAL out1_r_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out1_g_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out1_b_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out1_r_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out1_g_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out1_b_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out2_r_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out2_g_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out2_b_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out2_r_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out2_g_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out2_b_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out3_r_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out3_g_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out3_b_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out3_r_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out3_g_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out3_b_o    :   std_logic_vector(7 DOWNTO 0);




COMPONENT tri_block IS PORT
		( clk    : IN std_logic;
		  vcount : IN std_logic_vector(11 DOWNTO 0);
		  hcount : IN std_logic_vector(10 DOWNTO 0);
		  clken_fcount: IN std_logic;
		  pattern   : IN  std_logic_vector(3 DOWNTO 0);
		    distance:IN std_logic_vector(3  DOWNTO 0);
  distance1      : IN  std_logic_vector(3 DOWNTO 0);
  level1   : IN  std_logic_vector(7 DOWNTO 0);
  level2      : IN  std_logic_vector(7 DOWNTO 0);
   level3      : IN  std_logic_vector(7 DOWNTO 0);
		  out_r_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_g_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_b_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_r_o   : OUT std_logic_vector(7 DOWNTO 0);
		  out_g_o   : OUT std_logic_vector(7 DOWNTO 0);
		  out_b_o   : OUT std_logic_vector(7 DOWNTO 0))
;
END COMPONENT;
COMPONENT catch IS PORT
		( clk    : IN std_logic;
		  vcount : IN std_logic_vector(11 DOWNTO 0);
		  hcount : IN std_logic_vector(10 DOWNTO 0);
		  clken_fcount: IN std_logic;
		  pattern   : IN  std_logic_vector(3 DOWNTO 0);
		    distance:IN std_logic_vector(3  DOWNTO 0);
  distance1      : IN  std_logic_vector(3 DOWNTO 0);
  level1   : IN  std_logic_vector(7 DOWNTO 0);
  level2      : IN  std_logic_vector(7 DOWNTO 0);
   level3      : IN  std_logic_vector(7 DOWNTO 0);
		  out_r_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_g_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_b_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_r_o   : OUT std_logic_vector(7 DOWNTO 0);
		  out_g_o   : OUT std_logic_vector(7 DOWNTO 0);
		  out_b_o   : OUT std_logic_vector(7 DOWNTO 0))
;
END COMPONENT;
COMPONENT andor IS PORT
		( clk    : IN std_logic;
		  vcount : IN std_logic_vector(11 DOWNTO 0);
		  hcount : IN std_logic_vector(10 DOWNTO 0);
		  clken_fcount: IN std_logic;
		  pattern   : IN  std_logic_vector(3 DOWNTO 0);
		    distance:IN std_logic_vector(3  DOWNTO 0);
     distance1      : IN  std_logic_vector(3 DOWNTO 0);
    level1   : IN  std_logic_vector(7 DOWNTO 0);
    level2      : IN  std_logic_vector(7 DOWNTO 0);
      level3      : IN  std_logic_vector(7 DOWNTO 0);
		  out_r_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_g_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_b_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_r_o   : OUT std_logic_vector(7 DOWNTO 0);
		  out_g_o   : OUT std_logic_vector(7 DOWNTO 0);
		  out_b_o   : OUT std_logic_vector(7 DOWNTO 0))
;
END COMPONENT;
BEGIN
U1 : tri_block
	PORT MAP
	(
		 clk  =>  clk,
		 vcount => vcount,
		 hcount => hcount,
		 clken_fcount => clken_fcount,
		 pattern => pattern,
		 distance=> distance,
		 distance1 => distance1,
		 level1=>level1,
		 level2=>level2,
		 level3=>level3,
		 out_r_e  => out1_r_e,
		 out_g_e  => out1_g_e,
		 out_b_e  => out1_b_e,
		 out_r_o  => out1_r_o,
		 out_g_o  => out1_g_o,
		 out_b_o  => out1_b_o
	);
U2 : catch
	PORT MAP
	(
		 clk  =>  clk,
		 vcount => vcount,
		 hcount => hcount,
		 clken_fcount => clken_fcount,
		 pattern => pattern,
		 distance=> distance,
		 distance1 =>distance1,
		 level1=>level1,
		 level2=>level2,
		 level3=>level3,
		 out_r_e  => out2_r_e,
		 out_g_e  => out2_g_e,
		 out_b_e  => out2_b_e,
		 out_r_o  => out2_r_o,
		 out_g_o  => out2_g_o,
		 out_b_o  => out2_b_o
	);
U3 : andor
	PORT MAP
	(
		 clk  =>  clk,
		 vcount => vcount,
		 hcount => hcount,
		 clken_fcount => clken_fcount,
		 pattern => pattern,
		 distance=> distance,
		 distance1 =>distance1,
		 level1=>level1,
		 level2=>level2,
		 level3=>level3,
		 out_r_e  => out3_r_e,
		 out_g_e  => out3_g_e,
		 out_b_e  => out3_b_e,
		 out_r_o  => out3_r_o,
		 out_g_o  => out3_g_o,
		 out_b_o  => out3_b_o
	);
PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
CASE selection IS
	WHEN "01"=>
		out_r_e <= out1_r_e;
		out_b_e <= out1_b_e;
		out_g_e <= out1_g_e;
		out_r_o <= out1_r_o;
		out_b_o <= out1_b_o;
		out_g_o <= out1_g_o;
	WHEN "10"=>
		out_r_e <= out2_r_e;
		out_b_e <= out2_b_e;
		out_g_e <= out2_g_e;
		out_r_o <= out2_r_o;
		out_b_o <= out2_b_o;
		out_g_o <= out2_g_o;
	WHEN "11" =>
		out_r_e <= out3_r_e;
		out_b_e <= out3_b_e;
		out_g_e <= out3_g_e;
		out_r_o <= out3_r_o;
		out_b_o <= out3_b_o;
		out_g_o <= out3_g_o;
	WHEN OTHERS =>
	    out_r_e <= "00000000";
		out_b_e <= "00000000";
		out_g_e <= "00000000";
		out_r_o <= "00000000";
		out_b_o <= "00000000";
		out_g_o <= "00000000";
	
END CASE;
END IF;
END PROCESS;

END rtl;