rgb.vhd

可以受上位机控制的通过fpga的视频信号发生器程序

LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY rgb IS PORT
( clk    : IN std_logic;
  vcount : IN std_logic_vector(11 DOWNTO 0);
  hcount : IN std_logic_vector(10 DOWNTO 0);
  sel    : IN std_logic;
  level1 : IN std_logic_vector(7 DOWNTO 0);
  out_r_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_g_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_b_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_r_o   : OUT std_logic_vector(7 DOWNTO 0);
  out_g_o   : OUT std_logic_vector(7 DOWNTO 0);
  out_b_o   : OUT std_logic_vector(7 DOWNTO 0));
CONSTANT HAC:integer:=512;   -- horizontal active pixels 1448*1151
CONSTANT HSY:integer:=68;     -- horizontal sync width (negative polarity)
CONSTANT HBP:integer:=80;     -- horizontal back porch
CONSTANT VAC:integer:=768;    -- vertical active pixels
CONSTANT VSY:integer:=6;      -- vertical sync width (negative polarity)
CONSTANT VBP:integer:=29;     -- vertical back porch

END rgb;

ARCHITECTURE rtl OF rgb IS
signal value:std_logic_vector(7 DOWNTO 0);
begin
process(clk)
begin
IF clk'event AND clk='1' THEN
if  vcount<VBP+VSY+160 AND hcount>=0 AND hcount<HBP+HSY+100
then value<="00000010";
elsif  vcount<VBP+VSY+160 AND hcount>=HBP+HSY+100 AND hcount<HBP+HSY+200
then value<="00000100";
elsif  vcount<VBP+VSY+160 AND hcount>=HBP+HSY+200 AND hcount<HBP+HSY+320
then value<="00000110";
elsif  vcount<VBP+VSY+160 AND hcount>=HBP+HSY+320 AND hcount<HBP+HSY+440
then value<="00001000";
elsif  vcount<VBP+VSY+160 AND hcount>=HBP+HSY+440 AND hcount<HBP+HSY+540
then value<="00001010";
elsif  vcount<VBP+VSY+160 AND hcount>=HBP+HSY+540 
then value<="00001100";

elsif vcount>=VBP+VSY+320 AND vcount<VBP+VSY+512 AND hcount>=0 AND hcount<HBP+HSY+100
then value<="00001110";
elsif vcount>=VBP+VSY+320 AND vcount<VBP+VSY+512 AND hcount>=HBP+HSY+100 AND hcount<HBP+HSY+200
then value<="00010000";
elsif vcount>=VBP+VSY+320 AND vcount<VBP+VSY+512 AND hcount>=HBP+HSY+200 AND hcount<HBP+HSY+320
then value<="00010010";
elsif vcount>=VBP+VSY+320 AND vcount<VBP+VSY+512 AND hcount>=HBP+HSY+320 AND hcount<HBP+HSY+440
then value<="00010100";
elsif vcount>=VBP+VSY+320 AND vcount<VBP+VSY+512 AND hcount>=HBP+HSY+440 AND hcount<HBP+HSY+540
then value<="00010110";
elsif vcount>=VBP+VSY+320 AND vcount<VBP+VSY+512 AND hcount>=HBP+HSY+540 
then value<="00011000";

elsif vcount>=VBP+VSY+512 AND vcount<VBP+VSY+704 AND hcount>=0 AND hcount<HBP+HSY+100
then value<="11101011";
elsif vcount>=VBP+VSY+512 AND vcount<VBP+VSY+704 AND hcount>=HBP+HSY+100 AND hcount<HBP+HSY+200
then value<="11101101";
elsif vcount>=VBP+VSY+512 AND vcount<VBP+VSY+704 AND hcount>=HBP+HSY+200 AND hcount<HBP+HSY+320
then value<="11101111";
elsif vcount>=VBP+VSY+512 AND vcount<VBP+VSY+704 AND hcount>=HBP+HSY+320 AND hcount<HBP+HSY+440
then value<="11110001";
elsif vcount>=VBP+VSY+512 AND vcount<VBP+VSY+704 AND hcount>=HBP+HSY+440 AND hcount<HBP+HSY+540
then value<="11110011";
elsif vcount>=VBP+VSY+512 AND vcount<VBP+VSY+704 AND hcount>=HBP+HSY+540 
then value<="11110101";

elsif vcount>=VBP+VSY+864  AND hcount>=0 AND hcount<HBP+HSY+100
then value<="11111001";
elsif vcount>=VBP+VSY+864  AND hcount>=HBP+HSY+100 AND hcount<HBP+HSY+200
then value<="11111010";
elsif vcount>=VBP+VSY+864  AND hcount>=HBP+HSY+200 AND hcount<HBP+HSY+320
then value<="11111011";
elsif vcount>=VBP+VSY+864  AND hcount>=HBP+HSY+320 AND hcount<HBP+HSY+440
then value<="11111100";
elsif vcount>=VBP+VSY+864  AND hcount>=HBP+HSY+440 AND hcount<HBP+HSY+540
then value<="11111101";
elsif vcount>=VBP+VSY+864  AND hcount>=HBP+HSY+540 
then value<="11111110";

elsif vcount>=VBP+VSY+160 and vcount<VBP+VSY+320
then value<="00000000";
elsif vcount>=VBP+VSY+704 and vcount<VBP+VSY+864
then value<="11111111";
end if;
end if;
end process;

out_r_e<=value when sel='0' else level1;
out_g_e<=value when sel='0' else level1;
out_b_e<=value when sel='0' else level1;
out_r_o<=value when sel='0' else level1;
out_g_o<=value when sel='0' else level1;
out_b_o<=value when sel='0' else level1;

end rtl;