image.tan.qmsg

可以受上位机控制的通过fpga的视频信号发生器程序

{ "Info" "ITDB_FULL_TPD_RESULT" "clk clk_out 4.267 ns Longest " "Info: Longest tpd from source pin \"clk\" to destination pin \"clk_out\" is 4.267 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_J4 2591 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_J4; Fanout = 2591; CLK Node = 'clk'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "" { clk } "NODE_NAME" } "" } } { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.515 ns) + CELL(1.622 ns) 4.267 ns clk_out 2 PIN PIN_B14 0 " "Info: 2: + IC(1.515 ns) + CELL(1.622 ns) = 4.267 ns; Loc. = PIN_B14; Fanout = 0; PIN Node = 'clk_out'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "3.137 ns" { clk clk_out } "NODE_NAME" } "" } } { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.752 ns 64.49 % " "Info: Total cell delay = 2.752 ns ( 64.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.515 ns 35.51 % " "Info: Total interconnect delay = 1.515 ns ( 35.51 % )" {  } {  } 0}  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "4.267 ns" { clk clk_out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.267 ns" { clk clk~out0 clk_out } { 0.000ns 0.000ns 1.515ns } { 0.000ns 1.130ns 1.622ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|medianFilter:sdaMedian\|shiftReg\[0\] sda clk 5.869 ns register " "Info: th for register \"expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|medianFilter:sdaMedian\|shiftReg\[0\]\" (data pin = \"sda\", clock pin = \"clk\") is 5.869 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.484 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 11.484 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_J4 2591 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_J4; Fanout = 2591; CLK Node = 'clk'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "" { clk } "NODE_NAME" } "" } } { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.793 ns) + CELL(0.720 ns) 2.643 ns moving_object:U1\|count1\[0\] 2 REG LC_X22_Y20_N1 6 " "Info: 2: + IC(0.793 ns) + CELL(0.720 ns) = 2.643 ns; Loc. = LC_X22_Y20_N1; Fanout = 6; REG Node = 'moving_object:U1\|count1\[0\]'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "1.513 ns" { clk moving_object:U1|count1[0] } "NODE_NAME" } "" } } { "moving_object.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/moving_object.vhd" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.626 ns) + CELL(0.720 ns) 6.989 ns expander:i2c_expander\|klok_div_8\[1\] 3 REG LC_X61_Y16_N5 2 " "Info: 3: + IC(3.626 ns) + CELL(0.720 ns) = 6.989 ns; Loc. = LC_X61_Y16_N5; Fanout = 2; REG Node = 'expander:i2c_expander\|klok_div_8\[1\]'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "4.346 ns" { moving_object:U1|count1[0] expander:i2c_expander|klok_div_8[1] } "NODE_NAME" } "" } } { "expander.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/expander.tdf" 29 11 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.438 ns) + CELL(0.720 ns) 8.147 ns expander:i2c_expander\|klok_div_8\[2\] 4 REG LC_X61_Y16_N2 52 " "Info: 4: + IC(0.438 ns) + CELL(0.720 ns) = 8.147 ns; Loc. = LC_X61_Y16_N2; Fanout = 52; REG Node = 'expander:i2c_expander\|klok_div_8\[2\]'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "1.158 ns" { expander:i2c_expander|klok_div_8[1] expander:i2c_expander|klok_div_8[2] } "NODE_NAME" } "" } } { "expander.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/expander.tdf" 29 11 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.790 ns) + CELL(0.547 ns) 11.484 ns expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|medianFilter:sdaMedian\|shiftReg\[0\] 5 REG LC_X10_Y4_N2 1 " "Info: 5: + IC(2.790 ns) + CELL(0.547 ns) = 11.484 ns; Loc. = LC_X10_Y4_N2; Fanout = 1; REG Node = 'expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|medianFilter:sdaMedian\|shiftReg\[0\]'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "3.337 ns" { expander:i2c_expander|klok_div_8[2] expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sdaMedian|shiftReg[0] } "NODE_NAME" } "" } } { "medianfilter.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/medianfilter.tdf" 18 12 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.837 ns 33.41 % " "Info: Total cell delay = 3.837 ns ( 33.41 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.647 ns 66.59 % " "Info: Total interconnect delay = 7.647 ns ( 66.59 % )" {  } {  } 0}  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "11.484 ns" { clk moving_object:U1|count1[0] expander:i2c_expander|klok_div_8[1] expander:i2c_expander|klok_div_8[2] expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sdaMedian|shiftReg[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.484 ns" { clk clk~out0 moving_object:U1|count1[0] expander:i2c_expander|klok_div_8[1] expander:i2c_expander|klok_div_8[2] expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sdaMedian|shiftReg[0] } { 0.000ns 0.000ns 0.793ns 3.626ns 0.438ns 2.790ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.720ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "medianfilter.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/medianfilter.tdf" 18 12 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.627 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.627 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sda 1 PIN PIN_T4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_T4; Fanout = 1; PIN Node = 'sda'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "" { sda } "NODE_NAME" } "" } } { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns expander:i2c_expander\|sda~0 2 COMB IOC_X4_Y0_N1 6 " "Info: 2: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = IOC_X4_Y0_N1; Fanout = 6; COMB Node = 'expander:i2c_expander\|sda~0'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "1.135 ns" { sda expander:i2c_expander|sda~0 } "NODE_NAME" } "" } } { "expander.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/expander.tdf" 55 1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.403 ns) + CELL(0.089 ns) 5.627 ns expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|medianFilter:sdaMedian\|shiftReg\[0\] 3 REG LC_X10_Y4_N2 1 " "Info: 3: + IC(4.403 ns) + CELL(0.089 ns) = 5.627 ns; Loc. = LC_X10_Y4_N2; Fanout = 1; REG Node = 'expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|medianFilter:sdaMedian\|shiftReg\[0\]'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "4.492 ns" { expander:i2c_expander|sda~0 expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sdaMedian|shiftReg[0] } "NODE_NAME" } "" } } { "medianfilter.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/medianfilter.tdf" 18 12 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.224 ns 21.75 % " "Info: Total cell delay = 1.224 ns ( 21.75 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.403 ns 78.25 % " "Info: Total interconnect delay = 4.403 ns ( 78.25 % )" {  } {  } 0}  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "5.627 ns" { sda expander:i2c_expander|sda~0 expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sdaMedian|shiftReg[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.627 ns" { sda expander:i2c_expander|sda~0 expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sdaMedian|shiftReg[0] } { 0.000ns 0.000ns 4.403ns } { 0.000ns 1.135ns 0.089ns } } }  } 0}  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Progra