image.tan.qmsg

可以受上位机控制的通过fpga的视频信号发生器程序

{ "Info" "ITDB_TSU_RESULT" "expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|medianFilter:sclMedian\|sum\[1\] scl clk -4.407 ns register " "Info: tsu for register \"expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|medianFilter:sclMedian\|sum\[1\]\" (data pin = \"scl\", clock pin = \"clk\") is -4.407 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.048 ns + Longest pin register " "Info: + Longest pin to register delay is 7.048 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns scl 1 PIN PIN_T6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_T6; Fanout = 1; PIN Node = 'scl'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "" { scl } "NODE_NAME" } "" } } { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns expander:i2c_expander\|scl~0 2 COMB IOC_X14_Y0_N1 5 " "Info: 2: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = IOC_X14_Y0_N1; Fanout = 5; COMB Node = 'expander:i2c_expander\|scl~0'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "1.135 ns" { scl expander:i2c_expander|scl~0 } "NODE_NAME" } "" } } { "expander.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/expander.tdf" 54 1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.777 ns) + CELL(0.225 ns) 6.137 ns expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|medianFilter:sclMedian\|_~181 3 COMB LC_X25_Y4_N7 2 " "Info: 3: + IC(4.777 ns) + CELL(0.225 ns) = 6.137 ns; Loc. = LC_X25_Y4_N7; Fanout = 2; COMB Node = 'expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|medianFilter:sclMedian\|_~181'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "5.002 ns" { expander:i2c_expander|scl~0 expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sclMedian|_~181 } "NODE_NAME" } "" } } { "i2cslave.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/i2cslave.tdf" 156 4 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.568 ns) 7.048 ns expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|medianFilter:sclMedian\|sum\[1\] 4 REG LC_X25_Y4_N3 4 " "Info: 4: + IC(0.343 ns) + CELL(0.568 ns) = 7.048 ns; Loc. = LC_X25_Y4_N3; Fanout = 4; REG Node = 'expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|medianFilter:sclMedian\|sum\[1\]'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "0.911 ns" { expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sclMedian|_~181 expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sclMedian|sum[1] } "NODE_NAME" } "" } } { "medianfilter.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/medianfilter.tdf" 19 7 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.928 ns 27.36 % " "Info: Total cell delay = 1.928 ns ( 27.36 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.120 ns 72.64 % " "Info: Total interconnect delay = 5.120 ns ( 72.64 % )" {  } {  } 0}  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "7.048 ns" { scl expander:i2c_expander|scl~0 expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sclMedian|_~181 expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sclMedian|sum[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.048 ns" { scl expander:i2c_expander|scl~0 expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sclMedian|_~181 expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sclMedian|sum[1] } { 0.000ns 0.000ns 4.777ns 0.343ns } { 0.000ns 1.135ns 0.225ns 0.568ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "medianfilter.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/medianfilter.tdf" 19 7 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.484 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 11.484 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_J4 2591 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_J4; Fanout = 2591; CLK Node = 'clk'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "" { clk } "NODE_NAME" } "" } } { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.793 ns) + CELL(0.720 ns) 2.643 ns moving_object:U1\|count1\[0\] 2 REG LC_X22_Y20_N1 6 " "Info: 2: + IC(0.793 ns) + CELL(0.720 ns) = 2.643 ns; Loc. = LC_X22_Y20_N1; Fanout = 6; REG Node = 'moving_object:U1\|count1\[0\]'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "1.513 ns" { clk moving_object:U1|count1[0] } "NODE_NAME" } "" } } { "moving_object.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/moving_object.vhd" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.626 ns) + CELL(0.720 ns) 6.989 ns expander:i2c_expander\|klok_div_8\[1\] 3 REG LC_X61_Y16_N5 2 " "Info: 3: + IC(3.626 ns) + CELL(0.720 ns) = 6.989 ns; Loc. = LC_X61_Y16_N5; Fanout = 2; REG Node = 'expander:i2c_expander\|klok_div_8\[1\]'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "4.346 ns" { moving_object:U1|count1[0] expander:i2c_expander|klok_div_8[1] } "NODE_NAME" } "" } } { "expander.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/expander.tdf" 29 11 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.438 ns) + CELL(0.720 ns) 8.147 ns expander:i2c_expander\|klok_div_8\[2\] 4 REG LC_X61_Y16_N2 52 " "Info: 4: + IC(0.438 ns) + CELL(0.720 ns) = 8.147 ns; Loc. = LC_X61_Y16_N2; Fanout = 52; REG Node = 'expander:i2c_expander\|klok_div_8\[2\]'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "1.158 ns" { expander:i2c_expander|klok_div_8[1] expander:i2c_expander|klok_div_8[2] } "NODE_NAME" } "" } } { "expander.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/expander.tdf" 29 11 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.790 ns) + CELL(0.547 ns) 11.484 ns expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|medianFilter:sclMedian\|sum\[1\] 5 REG LC_X25_Y4_N3 4 " "Info: 5: + IC(2.790 ns) + CELL(0.547 ns) = 11.484 ns; Loc. = LC_X25_Y4_N3; Fanout = 4; REG Node = 'expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|medianFilter:sclMedian\|sum\[1\]'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "3.337 ns" { expander:i2c_expander|klok_div_8[2] expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sclMedian|sum[1] } "NODE_NAME" } "" } } { "medianfilter.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/medianfilter.tdf" 19 7 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.837 ns 33.41 % " "Info: Total cell delay = 3.837 ns ( 33.41 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.647 ns 66.59 % " "Info: Total interconnect delay = 7.647 ns ( 66.59 % )" {  } {  } 0}  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "11.484 ns" { clk moving_object:U1|count1[0] expander:i2c_expander|klok_div_8[1] expander:i2c_expander|klok_div_8[2] expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sclMedian|sum[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.484 ns" { clk clk~out0 moving_object:U1|count1[0] expander:i2c_expander|klok_div_8[1] expander:i2c_expander|klok_div_8[2] expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sclMedian|sum[1] } { 0.000ns 0.000ns 0.793ns 3.626ns 0.438ns 2.790ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.720ns 0.547ns } } }  } 0}  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "7.048 ns" { scl expander:i2c_expander|scl~0 expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sclMedian|_~181 expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sclMedian|sum[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.048 ns" { scl expander:i2c_expander|scl~0 expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sclMedian|_~181 expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sclMedian|sum[1] } { 0.000ns 0.000ns 4.777ns 0.343ns } { 0.000ns 1.135ns 0.225ns 0.568ns } } } { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "11.484 ns" { clk moving_object:U1|count1[0] expander:i2c_expander|klok_div_8[1] expander:i2c_expander|klok_div_8[2] expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sclMedian|sum[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.484 ns" { clk clk~out0 moving_object:U1|count1[0] expander:i2c_expander|klok_div_8[1] expander:i2c_expander|klok_div_8[2] expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sclMedian|sum[1] } { 0.000ns 0.000ns 0.793ns 3.626ns 0.438ns 2.790ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.720ns 0.547ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk sda expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|bitCounter\[2\] 21.015 ns register " "Info: tco from clock \"clk\" to destination pin \"sda\" through register \"expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|bitCounter\[2\]\" is 21.015 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 11.409 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 11.409 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_J4 2591 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_J4; Fanout = 2591; CLK Node = 'clk'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "" { clk } "NODE_NAME" } "" } } { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.793 ns) + CELL(0.720 ns) 2.643 ns moving_object:U1\|count1\[0\] 2 REG LC_X22_Y20_N1 6 " "Info: 2: + IC(0.793 ns) + CELL(0.720 ns) = 2.643 ns; Loc. = LC_X22_Y20_N1; Fanout = 6; REG Node = 'moving_object:U1\|count1\[0\]'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "1.513 ns" { clk moving_object:U1|count1[0] } "NODE_NAME" } "" } } { "moving_object.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/moving_object.vhd" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.626 ns) + CELL(0.720 ns) 6.989 ns expander:i2c_expander\|klok_div_8\[1\] 3 REG LC_X61_Y16_N5 2 " "Info: 3: + IC(3.626 ns) + CELL(0.720 ns) = 6.989 ns; Loc. = LC_X61_Y16_N5; Fanout = 2; REG Node = 'expander:i2c_expander\|klok_div_8\[1\]'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "4.346 ns" { moving_object:U1|count1[0] expander:i2c_expander|klok_div_8[1] } "NODE_NAME" } "" } } { "expander.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/expander.tdf" 29 11 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.438 ns) + CELL(0.720 ns) 8.147 ns expander:i2c_expander\|klok_div_8\[2\] 4 REG LC_X61_Y16_N2 52 " "Info: 4: + IC(0.438 ns) + CELL(0.720 ns) = 8.147 ns; Loc. = LC_X61_Y16_N2; Fanout = 52; REG Node = 'expander:i2c_expander\|klok_div_8\[2\]'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "1.158 ns" { expander:i2c_expander|klok_div_8[1] expander:i2c_expander|klok_div_8[2] } "NODE_NAME" } "" } } { "expander.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/expander.tdf" 29 11 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.715 ns) + CELL(0.547 ns) 11.409 ns expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|bitCounter\[2\] 5 REG LC_X46_Y14_N6 7 " "Info: 5: + IC(2.715 ns) + CELL(0.547 ns) = 11.409 ns; Loc. = LC_X46_Y14_N6; Fanout = 7; REG Node = 'expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|bitCounter\[2\]'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "3.262 ns" { expander:i2c_expander|klok_div_8[2] expander:i2c_expander|i2cSlave:I2Cslavecore_one|bitCounter[2] } "NODE_NAME" } "" } } { "i2cslave.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/i2cslave.tdf" 144 14 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.837 ns 33.63 % " "Info: Total cell delay = 3.837 ns ( 33.63 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.572 ns 66.37 % " "Info: Total interconnect delay = 7.572 ns ( 66.37 % )" {  } {  } 0}  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "11.409 ns" { clk moving_object:U1|count1[0] expander:i2c_expander|klok_div_8[1] expander:i2c_expander|klok_div_8[2] expander:i2c_expander|i2cSlave:I2Cslavecore_one|bitCounter[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.409 ns" { clk clk~out0 moving_object:U1|count1[0] expander:i2c_expander|klok_div_8[1] expander:i2c_expander|klok_div_8[2] expander:i2c_expander|i2cSlave:I2Cslavecore_one|bitCounter[2] } { 0.000ns 0.000ns 0.793ns 3.626ns 0.438ns 2.715ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.720ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "i2cslave.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/i2cslave.tdf" 144 14 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.433 ns + Longest register pin " "Info: + Longest register to pin delay is 9.433 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|bitCounter\[2\] 1 REG LC_X46_Y14_N6 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X46_Y14_N6; Fanout = 7; REG Node = 'expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|bitCounter\[2\]'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "" { expander:i2c_expander|i2cSlave:I2Cslavecore_one|bitCounter[2] } "NODE_NAME" } "" } } { "i2cslave.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/i2cslave.tdf" 144 14 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.048 ns) + CELL(0.454 ns) 1.502 ns expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|_~355 2 COMB LC_X46_Y15_N4 4 " "Info: 2: + IC(1.048 ns) + CELL(0.454 ns) = 1.502 ns; Loc. = LC_X46_Y15_N4; Fanout = 4; COMB Node = 'expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|_~355'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "1.502 ns" { expander:i2c_expander|i2cSlave:I2Cslavecore_one|bitCounter[2] expander:i2c_expander|i2cSlave:I2Cslavecore_one|_~355 } "NODE_NAME" } "" } } { "expander.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/expander.tdf" 27 1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.951 ns) + CELL(0.454 ns) 2.907 ns expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|forceSdaLow~292 3 COMB LC_X45_Y13_N2 1 " "Info: 3: + IC(0.951 ns) + CELL(0.454 ns) = 2.907 ns; Loc. = LC_X45_Y13_N2; Fanout = 1; COMB Node = 'expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|forceSdaLow~292'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "1.405 ns" { expander:i2c_expander|i2cSlave:I2Cslavecore_one|_~355 expander:i2c_expander|i2cSlave:I2Cslavecore_one|forceSdaLow~292 } "NODE_NAME" } "" } } { "i2cslave.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/i2cslave.tdf" 334 1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.904 ns) + CELL(1.622 ns) 9.433 ns sda 4 PIN PIN_T4 0 " "Info: 4: + IC(4.904 ns) + CELL(1.622 ns) = 9.433 ns; Loc. = PIN_T4; Fanout = 0; PIN Node = 'sda'" {  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "6.526 ns" { expander:i2c_expander|i2cSlave:I2Cslavecore_one|forceSdaLow~292 sda } "NODE_NAME" } "" } } { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.530 ns 26.82 % " "Info: Total cell delay = 2.530 ns ( 26.82 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.903 ns 73.18 % " "Info: Total interconnect delay = 6.903 ns ( 73.18 % )" {  } {  } 0}  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "9.433 ns" { expander:i2c_expander|i2cSlave:I2Cslavecore_one|bitCounter[2] expander:i2c_expander|i2cSlave:I2Cslavecore_one|_~355 expander:i2c_expander|i2cSlave:I2Cslavecore_one|forceSdaLow~292 sda } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.433 ns" { expander:i2c_expander|i2cSlave:I2Cslavecore_one|bitCounter[2] expander:i2c_expander|i2cSlave:I2Cslavecore_one|_~355 expander:i2c_expander|i2cSlave:I2Cslavecore_one|forceSdaLow~292 sda } { 0.000ns 1.048ns 0.951ns 4.904ns } { 0.000ns 0.454ns 0.454ns 1.622ns } } }  } 0}  } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "11.409 ns" { clk moving_object:U1|count1[0] expander:i2c_expander|klok_div_8[1] expander:i2c_expander|klok_div_8[2] expander:i2c_expander|i2cSlave:I2Cslavecore_one|bitCounter[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.409 ns" { clk clk~out0 moving_object:U1|count1[0] expander:i2c_expander|klok_div_8[1] expander:i2c_expander|klok_div_8[2] expander:i2c_expander|i2cSlave:I2Cslavecore_one|bitCounter[2] } { 0.000ns 0.000ns 0.793ns 3.626ns 0.438ns 2.715ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.720ns 0.547ns } } } { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "9.433 ns" { expander:i2c_expander|i2cSlave:I2Cslavecore_one|bitCounter[2] expander:i2c_expander|i2cSlave:I2Cslavecore_one|_~355 expander:i2c_expander|i2cSlave:I2Cslavecore_one|forceSdaLow~292 sda } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.433 ns" { expander:i2c_expander|i2cSlave:I2Cslavecore_one|bitCounter[2] expander:i2c_expander|i2cSlave:I2Cslavecore_one|_~355 expander:i2c_expander|i2cSlave:I2Cslavecore_one|forceSdaLow~292 sda } { 0.000ns 1.048ns 0.951ns 4.904ns } { 0.000ns 0.454ns 0.454ns 1.622ns } } }  } 0}