📄 image.tan.qmsg
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{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "moving_object:U1\|count1\[0\] " "Info: Detected ripple clock \"moving_object:U1\|count1\[0\]\" as buffer" { } { { "moving_object.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/moving_object.vhd" 49 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "moving_object:U1\|count1\[0\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "expander:i2c_expander\|klok_div_8\[1\] " "Info: Detected ripple clock \"expander:i2c_expander\|klok_div_8\[1\]\" as buffer" { } { { "expander.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/expander.tdf" 29 11 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "expander:i2c_expander\|klok_div_8\[1\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "expander:i2c_expander\|klok_div_8\[2\] " "Info: Detected ripple clock \"expander:i2c_expander\|klok_div_8\[2\]\" as buffer" { } { { "expander.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/expander.tdf" 29 11 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "expander:i2c_expander\|klok_div_8\[2\]" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register pos\[3\] register shinningblock:U2\|color 86.36 MHz 11.579 ns Internal " "Info: Clock \"clk\" has Internal fmax of 86.36 MHz between source register \"pos\[3\]\" and destination register \"shinningblock:U2\|color\" (period= 11.579 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.377 ns + Longest register register " "Info: + Longest register to register delay is 11.377 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pos\[3\] 1 REG LC_X24_Y16_N1 20 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X24_Y16_N1; Fanout = 20; REG Node = 'pos\[3\]'" { } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "" { pos[3] } "NODE_NAME" } "" } } { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 103 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.454 ns) 0.954 ns shinningblock:U2\|ypos\[5\]~127 2 COMB LC_X24_Y16_N5 12 " "Info: 2: + IC(0.500 ns) + CELL(0.454 ns) = 0.954 ns; Loc. = LC_X24_Y16_N5; Fanout = 12; COMB Node = 'shinningblock:U2\|ypos\[5\]~127'" { } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "0.954 ns" { pos[3] shinningblock:U2|ypos[5]~127 } "NODE_NAME" } "" } } { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 42 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.333 ns) 2.216 ns shinningblock:U2\|add~9904COUT1_10444 3 COMB LC_X24_Y15_N1 2 " "Info: 3: + IC(0.929 ns) + CELL(0.333 ns) = 2.216 ns; Loc. = LC_X24_Y15_N1; Fanout = 2; COMB Node = 'shinningblock:U2\|add~9904COUT1_10444'" { } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "1.262 ns" { shinningblock:U2|ypos[5]~127 shinningblock:U2|add~9904COUT1_10444 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.468 ns) 2.684 ns shinningblock:U2\|add~9787 4 COMB LC_X24_Y15_N2 3 " "Info: 4: + IC(0.000 ns) + CELL(0.468 ns) = 2.684 ns; Loc. = LC_X24_Y15_N2; Fanout = 3; COMB Node = 'shinningblock:U2\|add~9787'" { } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "0.468 ns" { shinningblock:U2|add~9904COUT1_10444 shinningblock:U2|add~9787 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.520 ns) + CELL(0.333 ns) 3.537 ns shinningblock:U2\|add~9674COUT1_10476 5 COMB LC_X25_Y15_N3 2 " "Info: 5: + IC(0.520 ns) + CELL(0.333 ns) = 3.537 ns; Loc. = LC_X25_Y15_N3; Fanout = 2; COMB Node = 'shinningblock:U2\|add~9674COUT1_10476'" { } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "0.853 ns" { shinningblock:U2|add~9787 shinningblock:U2|add~9674COUT1_10476 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.468 ns) 4.005 ns shinningblock:U2\|add~9552 6 COMB LC_X25_Y15_N4 6 " "Info: 6: + IC(0.000 ns) + CELL(0.468 ns) = 4.005 ns; Loc. = LC_X25_Y15_N4; Fanout = 6; COMB Node = 'shinningblock:U2\|add~9552'" { } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "0.468 ns" { shinningblock:U2|add~9674COUT1_10476 shinningblock:U2|add~9552 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.333 ns) 5.267 ns shinningblock:U2\|add~9438COUT1_10696 7 COMB LC_X26_Y14_N2 2 " "Info: 7: + IC(0.929 ns) + CELL(0.333 ns) = 5.267 ns; Loc. = LC_X26_Y14_N2; Fanout = 2; COMB Node = 'shinningblock:U2\|add~9438COUT1_10696'" { } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "1.262 ns" { shinningblock:U2|add~9552 shinningblock:U2|add~9438COUT1_10696 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.468 ns) 5.735 ns shinningblock:U2\|add~9320 8 COMB LC_X26_Y14_N3 3 " "Info: 8: + IC(0.000 ns) + CELL(0.468 ns) = 5.735 ns; Loc. = LC_X26_Y14_N3; Fanout = 3; COMB Node = 'shinningblock:U2\|add~9320'" { } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "0.468 ns" { shinningblock:U2|add~9438COUT1_10696 shinningblock:U2|add~9320 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.538 ns) + CELL(0.443 ns) 6.716 ns shinningblock:U2\|add~9212COUT1_10494 9 COMB LC_X27_Y14_N7 2 " "Info: 9: + IC(0.538 ns) + CELL(0.443 ns) = 6.716 ns; Loc. = LC_X27_Y14_N7; Fanout = 2; COMB Node = 'shinningblock:U2\|add~9212COUT1_10494'" { } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "0.981 ns" { shinningblock:U2|add~9320 shinningblock:U2|add~9212COUT1_10494 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.468 ns) 7.184 ns shinningblock:U2\|add~9119 10 COMB LC_X27_Y14_N8 1 " "Info: 10: + IC(0.000 ns) + CELL(0.468 ns) = 7.184 ns; Loc. = LC_X27_Y14_N8; Fanout = 1; COMB Node = 'shinningblock:U2\|add~9119'" { } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "0.468 ns" { shinningblock:U2|add~9212COUT1_10494 shinningblock:U2|add~9119 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.845 ns) + CELL(0.449 ns) 8.478 ns shinningblock:U2\|LessThan~2058 11 COMB LC_X29_Y14_N4 1 " "Info: 11: + IC(0.845 ns) + CELL(0.449 ns) = 8.478 ns; Loc. = LC_X29_Y14_N4; Fanout = 1; COMB Node = 'shinningblock:U2\|LessThan~2058'" { } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "1.294 ns" { shinningblock:U2|add~9119 shinningblock:U2|LessThan~2058 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.478 ns) 8.956 ns shinningblock:U2\|LessThan~1996 12 COMB LC_X29_Y14_N5 1 " "Info: 12: + IC(0.000 ns) + CELL(0.478 ns) = 8.956 ns; Loc. = LC_X29_Y14_N5; Fanout = 1; COMB Node = 'shinningblock:U2\|LessThan~1996'" { } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "0.478 ns" { shinningblock:U2|LessThan~2058 shinningblock:U2|LessThan~1996 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.976 ns) + CELL(0.225 ns) 10.157 ns shinningblock:U2\|process5~689 13 COMB LC_X28_Y17_N6 2 " "Info: 13: + IC(0.976 ns) + CELL(0.225 ns) = 10.157 ns; Loc. = LC_X28_Y17_N6; Fanout = 2; COMB Node = 'shinningblock:U2\|process5~689'" { } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "1.201 ns" { shinningblock:U2|LessThan~1996 shinningblock:U2|process5~689 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.140 ns) + CELL(0.088 ns) 10.385 ns shinningblock:U2\|process5~690 14 COMB LC_X28_Y17_N7 1 " "Info: 14: + IC(0.140 ns) + CELL(0.088 ns) = 10.385 ns; Loc. = LC_X28_Y17_N7; Fanout = 1; COMB Node = 'shinningblock:U2\|process5~690'" { } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "0.228 ns" { shinningblock:U2|process5~689 shinningblock:U2|process5~690 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.525 ns) + CELL(0.467 ns) 11.377 ns shinningblock:U2\|color 15 REG LC_X29_Y17_N8 8 " "Info: 15: + IC(0.525 ns) + CELL(0.467 ns) = 11.377 ns; Loc. = LC_X29_Y17_N8; Fanout = 8; REG Node = 'shinningblock:U2\|color'" { } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "0.992 ns" { shinningblock:U2|process5~690 shinningblock:U2|color } "NODE_NAME" } "" } } { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 43 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.475 ns 48.12 % " "Info: Total cell delay = 5.475 ns ( 48.12 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.902 ns 51.88 % " "Info: Total interconnect delay = 5.902 ns ( 51.88 % )" { } { } 0} } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "11.377 ns" { pos[3] shinningblock:U2|ypos[5]~127 shinningblock:U2|add~9904COUT1_10444 shinningblock:U2|add~9787 shinningblock:U2|add~9674COUT1_10476 shinningblock:U2|add~9552 shinningblock:U2|add~9438COUT1_10696 shinningblock:U2|add~9320 shinningblock:U2|add~9212COUT1_10494 shinningblock:U2|add~9119 shinningblock:U2|LessThan~2058 shinningblock:U2|LessThan~1996 shinningblock:U2|process5~689 shinningblock:U2|process5~690 shinningblock:U2|color } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.377 ns" { pos[3] shinningblock:U2|ypos[5]~127 shinningblock:U2|add~9904COUT1_10444 shinningblock:U2|add~9787 shinningblock:U2|add~9674COUT1_10476 shinningblock:U2|add~9552 shinningblock:U2|add~9438COUT1_10696 shinningblock:U2|add~9320 shinningblock:U2|add~9212COUT1_10494 shinningblock:U2|add~9119 shinningblock:U2|LessThan~2058 shinningblock:U2|LessThan~1996 shinningblock:U2|process5~689 shinningblock:U2|process5~690 shinningblock:U2|color } { 0.000ns 0.500ns 0.929ns 0.000ns 0.520ns 0.000ns 0.929ns 0.000ns 0.538ns 0.000ns 0.845ns 0.000ns 0.976ns 0.140ns 0.525ns } { 0.000ns 0.454ns 0.333ns 0.468ns 0.333ns 0.468ns 0.333ns 0.468ns 0.443ns 0.468ns 0.449ns 0.478ns 0.225ns 0.088ns 0.467ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.440 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.440 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_J4 2591 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_J4; Fanout = 2591; CLK Node = 'clk'" { } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "" { clk } "NODE_NAME" } "" } } { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.763 ns) + CELL(0.547 ns) 2.440 ns shinningblock:U2\|color 2 REG LC_X29_Y17_N8 8 " "Info: 2: + IC(0.763 ns) + CELL(0.547 ns) = 2.440 ns; Loc. = LC_X29_Y17_N8; Fanout = 8; REG Node = 'shinningblock:U2\|color'" { } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "1.310 ns" { clk shinningblock:U2|color } "NODE_NAME" } "" } } { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 43 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 68.73 % " "Info: Total cell delay = 1.677 ns ( 68.73 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.763 ns 31.27 % " "Info: Total interconnect delay = 0.763 ns ( 31.27 % )" { } { } 0} } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "2.440 ns" { clk shinningblock:U2|color } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.440 ns" { clk clk~out0 shinningblock:U2|color } { 0.000ns 0.000ns 0.763ns } { 0.000ns 1.130ns 0.547ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.440 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.440 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_J4 2591 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_J4; Fanout = 2591; CLK Node = 'clk'" { } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "" { clk } "NODE_NAME" } "" } } { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.763 ns) + CELL(0.547 ns) 2.440 ns pos\[3\] 2 REG LC_X24_Y16_N1 20 " "Info: 2: + IC(0.763 ns) + CELL(0.547 ns) = 2.440 ns; Loc. = LC_X24_Y16_N1; Fanout = 20; REG Node = 'pos\[3\]'" { } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "1.310 ns" { clk pos[3] } "NODE_NAME" } "" } } { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 103 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 68.73 % " "Info: Total cell delay = 1.677 ns ( 68.73 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.763 ns 31.27 % " "Info: Total interconnect delay = 0.763 ns ( 31.27 % )" { } { } 0} } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "2.440 ns" { clk pos[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.440 ns" { clk clk~out0 pos[3] } { 0.000ns 0.000ns 0.763ns } { 0.000ns 1.130ns 0.547ns } } } } 0} } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "2.440 ns" { clk shinningblock:U2|color } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.440 ns" { clk clk~out0 shinningblock:U2|color } { 0.000ns 0.000ns 0.763ns } { 0.000ns 1.130ns 0.547ns } } } { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "2.440 ns" { clk pos[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.440 ns" { clk clk~out0 pos[3] } { 0.000ns 0.000ns 0.763ns } { 0.000ns 1.130ns 0.547ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" { } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 103 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" { } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 43 -1 0 } } } 0} } { { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "11.377 ns" { pos[3] shinningblock:U2|ypos[5]~127 shinningblock:U2|add~9904COUT1_10444 shinningblock:U2|add~9787 shinningblock:U2|add~9674COUT1_10476 shinningblock:U2|add~9552 shinningblock:U2|add~9438COUT1_10696 shinningblock:U2|add~9320 shinningblock:U2|add~9212COUT1_10494 shinningblock:U2|add~9119 shinningblock:U2|LessThan~2058 shinningblock:U2|LessThan~1996 shinningblock:U2|process5~689 shinningblock:U2|process5~690 shinningblock:U2|color } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "11.377 ns" { pos[3] shinningblock:U2|ypos[5]~127 shinningblock:U2|add~9904COUT1_10444 shinningblock:U2|add~9787 shinningblock:U2|add~9674COUT1_10476 shinningblock:U2|add~9552 shinningblock:U2|add~9438COUT1_10696 shinningblock:U2|add~9320 shinningblock:U2|add~9212COUT1_10494 shinningblock:U2|add~9119 shinningblock:U2|LessThan~2058 shinningblock:U2|LessThan~1996 shinningblock:U2|process5~689 shinningblock:U2|process5~690 shinningblock:U2|color } { 0.000ns 0.500ns 0.929ns 0.000ns 0.520ns 0.000ns 0.929ns 0.000ns 0.538ns 0.000ns 0.845ns 0.000ns 0.976ns 0.140ns 0.525ns } { 0.000ns 0.454ns 0.333ns 0.468ns 0.333ns 0.468ns 0.333ns 0.468ns 0.443ns 0.468ns 0.449ns 0.478ns 0.225ns 0.088ns 0.467ns } } } { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "2.440 ns" { clk shinningblock:U2|color } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.440 ns" { clk clk~out0 shinningblock:U2|color } { 0.000ns 0.000ns 0.763ns } { 0.000ns 1.130ns 0.547ns } } } { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "2.440 ns" { clk pos[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.440 ns" { clk clk~out0 pos[3] } { 0.000ns 0.000ns 0.763ns } { 0.000ns 1.130ns 0.547ns } } } } 0}
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