image.fit.qmsg

可以受上位机控制的通过fpga的视频信号发生器程序

{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: The following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "pixs_out VCC " "Info: Pin pixs_out has VCC driving its datain port" {  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 13 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "pixs_out" } } } } { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "" { pixs_out } "NODE_NAME" } "" } } { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.fld" "" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.fld" "" "" { pixs_out } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: The following groups of pins have the same output enable" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|forceSdaLow~292 " "Info: The following pins have the same output enable: expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|forceSdaLow~292" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional sda LVTTL " "Info: Type bidirectional pin sda uses the LVTTL I/O standard" {  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 6 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sda" } } } } { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "" { sda } "NODE_NAME" } "" } } { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.fld" "" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.fld" "" "" { sda } "NODE_NAME" } }  } 0}  } {  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|waitff " "Info: The following pins have the same output enable: expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|waitff" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional scl LVTTL " "Info: Type bidirectional pin scl uses the LVTTL I/O standard" {  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 7 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "scl" } } } } { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "" { scl } "NODE_NAME" } "" } } { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.fld" "" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.fld" "" "" { scl } "NODE_NAME" } }  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 09 10:31:14 2007 " "Info: Processing ended: Thu Aug 09 10:31:14 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:01:37 " "Info: Elapsed time: 00:01:37" {  } {  } 0}  } {  } 0}