image.fit.qmsg

可以受上位机控制的通过fpga的视频信号发生器程序

{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_USER_GLOBAL_ASSIGNED" "logic cell expander:i2c_expander\|klok_div_8\[2\] " "Info: Promoted logic cell \"expander:i2c_expander\|klok_div_8\[2\]\" with Global Signal logic option assignment" { { "Info" "IFYGR_FYGR_USER_GLOBAL_ASSIGNED_REGION" "Global clock the entire device " "Info: Fan-outs that use the Global signal logic option setting Global clock are assigned to the entire device" {  } {  } 0}  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "expander:i2c_expander\|klok_div_8\[2\]" } } } } { "expander.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/expander.tdf" 29 11 0 } } { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "" { expander:i2c_expander|klok_div_8[2] } "NODE_NAME" } "" } } { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.fld" "" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.fld" "" "" { expander:i2c_expander|klok_div_8[2] } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clk Global clock in PIN J4 " "Info: Automatically promoted some destinations of signal \"clk\" to use Global clock in PIN J4" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clk_out " "Info: Destination \"clk_out\" may be non-global or may not use global clock" {  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 9 -1 0 } }  } 0}  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 8 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "startin Global clock " "Info: Automatically promoted some destinations of signal \"startin\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "shinningblock:U2\|trigger~1 " "Info: Destination \"shinningblock:U2\|trigger~1\" may be non-global or may not use global clock" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 22 -1 0 } }  } 0}  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 92 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "reduce_nor~218 Global clock " "Info: Automatically promoted signal \"reduce_nor~218\" to use Global clock" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "reduce_nor~218" } } } } { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "" { reduce_nor~218 } "NODE_NAME" } "" } } { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.fld" "" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.fld" "" "" { reduce_nor~218 } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "reduce_nor~0 Global clock " "Info: Automatically promoted signal \"reduce_nor~0\" to use Global clock" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "reduce_nor~0" } } } } { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "" { reduce_nor~0 } "NODE_NAME" } "" } } { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.fld" "" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.fld" "" "" { reduce_nor~0 } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "shinning:U3\|reduce_nor~67 Global clock " "Info: Automatically promoted signal \"shinning:U3\|reduce_nor~67\" to use Global clock" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "shinning:U3\|reduce_nor~67" } } } } { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" "" { Report "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/cyclic.quartus_db" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/" "" "" { shinning:U3|reduce_nor~67 } "NODE_NAME" } "" } } { "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.fld" "" { Floorplan "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.fld" "" "" { shinning:U3|reduce_nor~67 } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}