mux_vab.tdf

可以受上位机控制的通过fpga的视频信号发生器程序

--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" LPM_SIZE=2 LPM_WIDTH=8 LPM_WIDTHS=1 data result sel
--VERSION_BEGIN 5.0 cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ  VERSION_END


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--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 8 
SUBDESIGN mux_vab
( 
	data[15..0]	:	input;
	result[7..0]	:	output;
	sel[0..0]	:	input;
) 
VARIABLE 
	result_node[7..0]	: WIRE;
	sel_node[0..0]	: WIRE;
	w_data247w[1..0]	: WIRE;
	w_data261w[1..0]	: WIRE;
	w_data273w[1..0]	: WIRE;
	w_data285w[1..0]	: WIRE;
	w_data297w[1..0]	: WIRE;
	w_data309w[1..0]	: WIRE;
	w_data321w[1..0]	: WIRE;
	w_data333w[1..0]	: WIRE;
	w_result248w	: WIRE;
	w_result254w	: WIRE;
	w_result262w	: WIRE;
	w_result268w	: WIRE;
	w_result274w	: WIRE;
	w_result280w	: WIRE;
	w_result286w	: WIRE;
	w_result292w	: WIRE;
	w_result298w	: WIRE;
	w_result304w	: WIRE;
	w_result310w	: WIRE;
	w_result316w	: WIRE;
	w_result322w	: WIRE;
	w_result328w	: WIRE;
	w_result334w	: WIRE;
	w_result340w	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( w_result334w, w_result322w, w_result310w, w_result298w, w_result286w, w_result274w, w_result262w, w_result248w);
	sel_node[] = ( sel[0..0]);
	w_data247w[] = ( data[8..8], data[0..0]);
	w_data261w[] = ( data[9..9], data[1..1]);
	w_data273w[] = ( data[10..10], data[2..2]);
	w_data285w[] = ( data[11..11], data[3..3]);
	w_data297w[] = ( data[12..12], data[4..4]);
	w_data309w[] = ( data[13..13], data[5..5]);
	w_data321w[] = ( data[14..14], data[6..6]);
	w_data333w[] = ( data[15..15], data[7..7]);
	w_result248w = w_result254w;
	w_result254w = ((sel_node[] & w_data247w[1..1]) # ((! sel_node[]) & w_data247w[0..0]));
	w_result262w = w_result268w;
	w_result268w = ((sel_node[] & w_data261w[1..1]) # ((! sel_node[]) & w_data261w[0..0]));
	w_result274w = w_result280w;
	w_result280w = ((sel_node[] & w_data273w[1..1]) # ((! sel_node[]) & w_data273w[0..0]));
	w_result286w = w_result292w;
	w_result292w = ((sel_node[] & w_data285w[1..1]) # ((! sel_node[]) & w_data285w[0..0]));
	w_result298w = w_result304w;
	w_result304w = ((sel_node[] & w_data297w[1..1]) # ((! sel_node[]) & w_data297w[0..0]));
	w_result310w = w_result316w;
	w_result316w = ((sel_node[] & w_data309w[1..1]) # ((! sel_node[]) & w_data309w[0..0]));
	w_result322w = w_result328w;
	w_result328w = ((sel_node[] & w_data321w[1..1]) # ((! sel_node[]) & w_data321w[0..0]));
	w_result334w = w_result340w;
	w_result340w = ((sel_node[] & w_data333w[1..1]) # ((! sel_node[]) & w_data333w[0..0]));
END;
--VALID FILE