📄 image.map.qmsg

📁 可以受上位机控制的通过fpga的视频信号发生器程序
💻 QMSG
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{ "Info" "ISGN_SEARCH_FILE" "rom5.vhd 2 1 " "Info: Using design file rom5.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rom5-SYN " "Info: Found design unit 1: rom5-SYN" {  } { { "rom5.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/rom5.vhd" 51 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 rom5 " "Info: Found entity 1: rom5" {  } { { "rom5.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/rom5.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom5 moving_object:U1\|rom5:u8 " "Info: Elaborating entity \"rom5\" for hierarchy \"moving_object:U1\|rom5:u8\"" {  } { { "moving_object.vhd" "u8" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/moving_object.vhd" 377 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram moving_object:U1\|rom5:u8\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"moving_object:U1\|rom5:u8\|altsyncram:altsyncram_component\"" {  } { { "rom5.vhd" "altsyncram_component" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/rom5.vhd" 111 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_s5t1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_s5t1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_s5t1 " "Info: Found entity 1: altsyncram_s5t1" {  } { { "db/altsyncram_s5t1.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/altsyncram_s5t1.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_s5t1 moving_object:U1\|rom5:u8\|altsyncram:altsyncram_component\|altsyncram_s5t1:auto_generated " "Info: Elaborating entity \"altsyncram_s5t1\" for hierarchy \"moving_object:U1\|rom5:u8\|altsyncram:altsyncram_component\|altsyncram_s5t1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "rom6.vhd 2 1 " "Info: Using design file rom6.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rom6-SYN " "Info: Found design unit 1: rom6-SYN" {  } { { "rom6.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/rom6.vhd" 51 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 rom6 " "Info: Found entity 1: rom6" {  } { { "rom6.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/rom6.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom6 moving_object:U1\|rom6:u9 " "Info: Elaborating entity \"rom6\" for hierarchy \"moving_object:U1\|rom6:u9\"" {  } { { "moving_object.vhd" "u9" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/moving_object.vhd" 387 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram moving_object:U1\|rom6:u9\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"moving_object:U1\|rom6:u9\|altsyncram:altsyncram_component\"" {  } { { "rom6.vhd" "altsyncram_component" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/rom6.vhd" 111 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_t5t1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_t5t1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_t5t1 " "Info: Found entity 1: altsyncram_t5t1" {  } { { "db/altsyncram_t5t1.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/altsyncram_t5t1.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_t5t1 moving_object:U1\|rom6:u9\|altsyncram:altsyncram_component\|altsyncram_t5t1:auto_generated " "Info: Elaborating entity \"altsyncram_t5t1\" for hierarchy \"moving_object:U1\|rom6:u9\|altsyncram:altsyncram_component\|altsyncram_t5t1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shinningblock shinningblock:U2 " "Info: Elaborating entity \"shinningblock\" for hierarchy \"shinningblock:U2\"" {  } { { "image.vhd" "U2" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 412 -1 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "shiningblock.vhd(290) " "Info: VHDL Case Statement information at shiningblock.vhd(290): OTHERS choice is never selected" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 290 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shinning shinning:U3 " "Info: Elaborating entity \"shinning\" for hierarchy \"shinning:U3\"" {  } { { "image.vhd" "U3" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 440 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rgb rgb:u4 " "Info: Elaborating entity \"rgb\" for hierarchy \"rgb:u4\"" {  } { { "image.vhd" "u4" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 458 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "moving_object:U1\|address_a\[0\] data_in GND " "Warning: Reduced register \"moving_object:U1\|address_a\[0\]\" with stuck data_in port to stuck value GND" {  } { { "moving_object.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/moving_object.vhd" 42 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|address\[7\] data_in GND " "Warning: Reduced register \"expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|address\[7\]\" with stuck data_in port to stuck value GND" {  } { { "i2cslave.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/i2cslave.tdf" 149 11 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|address\[6\] data_in GND " "Warning: Reduced register \"expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|address\[6\]\" with stuck data_in port to stuck value GND" {  } { { "i2cslave.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/i2cslave.tdf" 149 11 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|address\[5\] data_in GND " "Warning: Reduced register \"expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|address\[5\]\" with stuck data_in port to stuck value GND" {  } { { "i2cslave.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/i2cslave.tdf" 149 11 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|address\[4\] data_in GND " "Warning: Reduced register \"expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|address\[4\]\" with stuck data_in port to stuck value GND" {  } { { "i2cslave.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/i2cslave.tdf" 149 11 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|address\[3\] data_in GND " "Warning: Reduced register \"expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|address\[3\]\" with stuck data_in port to stuck value GND" {  } { { "i2cslave.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/i2cslave.tdf" 149 11 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|address\[2\] data_in GND " "Warning: Reduced register \"expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|address\[2\]\" with stuck data_in port to stuck value GND" {  } { { "i2cslave.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/i2cslave.tdf" 149 11 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|address\[1\] data_in GND " "Warning: Reduced register \"expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|address\[1\]\" with stuck data_in port to stuck value GND" {  } { { "i2cslave.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/i2cslave.tdf" 149 11 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|address\[0\] data_in GND " "Warning: Reduced register \"expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|address\[0\]\" with stuck data_in port to stuck value GND" {  } { { "i2cslave.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/i2cslave.tdf" 149 11 0 } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_g_e\[7\] shinningblock:U2\|out1_r_e\[7\] " "Info: Duplicate register \"shinningblock:U2\|out1_g_e\[7\]\" merged to single register \"shinningblock:U2\|out1_r_e\[7\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 48 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_b_e\[7\] shinningblock:U2\|out1_r_e\[7\] " "Info: Duplicate register \"shinningblock:U2\|out1_b_e\[7\]\" merged to single register \"shinningblock:U2\|out1_r_e\[7\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 49 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_r_o\[7\] shinningblock:U2\|out1_r_e\[7\] " "Info: Duplicate register \"shinningblock:U2\|out1_r_o\[7\]\" merged to single register \"shinningblock:U2\|out1_r_e\[7\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 50 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_g_o\[7\] shinningblock:U2\|out1_r_e\[7\] " "Info: Duplicate register \"shinningblock:U2\|out1_g_o\[7\]\" merged to single register \"shinningblock:U2\|out1_r_e\[7\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 51 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_b_o\[7\] shinningblock:U2\|out1_r_e\[7\] " "Info: Duplicate register \"shinningblock:U2\|out1_b_o\[7\]\" merged to single register \"shinningblock:U2\|out1_r_e\[7\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 52 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_g_e\[6\] shinningblock:U2\|out1_r_e\[6\] " "Info: Duplicate register \"shinningblock:U2\|out1_g_e\[6\]\" merged to single register \"shinningblock:U2\|out1_r_e\[6\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 48 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_b_e\[6\] shinningblock:U2\|out1_r_e\[6\] " "Info: Duplicate register \"shinningblock:U2\|out1_b_e\[6\]\" merged to single register \"shinningblock:U2\|out1_r_e\[6\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 49 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_r_o\[6\] shinningblock:U2\|out1_r_e\[6\] " "Info: Duplicate register \"shinningblock:U2\|out1_r_o\[6\]\" merged to single register \"shinningblock:U2\|out1_r_e\[6\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 50 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_g_o\[6\] shinningblock:U2\|out1_r_e\[6\] " "Info: Duplicate register \"shinningblock:U2\|out1_g_o\[6\]\" merged to single register \"shinningblock:U2\|out1_r_e\[6\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 51 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_b_o\[6\] shinningblock:U2\|out1_r_e\[6\] " "Info: Duplicate register \"shinningblock:U2\|out1_b_o\[6\]\" merged to single register \"shinningblock:U2\|out1_r_e\[6\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 52 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_g_e\[5\] shinningblock:U2\|out1_r_e\[5\] " "Info: Duplicate register \"shinningblock:U2\|out1_g_e\[5\]\" merged to single register \"shinningblock:U2\|out1_r_e\[5\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 48 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_b_e\[5\] shinningblock:U2\|out1_r_e\[5\] " "Info: Duplicate register \"shinningblock:U2\|out1_b_e\[5\]\" merged to single register \"shinningblock:U2\|out1_r_e\[5\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 49 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_r_o\[5\] shinningblock:U2\|out1_r_e\[5\] " "Info: Duplicate register \"shinningblock:U2\|out1_r_o\[5\]\" merged to single register \"shinningblock:U2\|out1_r_e\[5\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 50 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_g_o\[5\] shinningblock:U2\|out1_r_e\[5\] " "Info: Duplicate register \"shinningblock:U2\|out1_g_o\[5\]\" merged to single register \"shinningblock:U2\|out1_r_e\[5\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 51 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_b_o\[5\] shinningblock:U2\|out1_r_e\[5\] " "Info: Duplicate register \"shinningblock:U2\|out1_b_o\[5\]\" merged to single register \"shinningblock:U2\|out1_r_e\[5\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 52 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_g_e\[4\] shinningblock:U2\|out1_r_e\[4\] " "Info: Duplicate register \"shinningblock:U2\|out1_g_e\[4\]\" merged to single register \"shinningblock:U2\|out1_r_e\[4\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 48 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_b_e\[4\] shinningblock:U2\|out1_r_e\[4\] " "Info: Duplicate register \"shinningblock:U2\|out1_b_e\[4\]\" merged to single register \"shinningblock:U2\|out1_r_e\[4\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 49 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_r_o\[4\] shinningblock:U2\|out1_r_e\[4\] " "Info: Duplicate register \"shinningblock:U2\|out1_r_o\[4\]\" merged to single register \"shinningblock:U2\|out1_r_e\[4\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 50 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_g_o\[4\] shinningblock:U2\|out1_r_e\[4\] " "Info: Duplicate register \"shinningblock:U2\|out1_g_o\[4\]\" merged to single register \"shinningblock:U2\|out1_r_e\[4\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 51 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_b_o\[4\] shinningblock:U2\|out1_r_e\[4\] " "Info: Duplicate register \"shinningblock:U2\|out1_b_o\[4\]\" merged to single register \"shinningblock:U2\|out1_r_e\[4\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 52 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_g_e\[3\] shinningblock:U2\|out1_r_e\[3\] " "Info: Duplicate register \"shinningblock:U2\|out1_g_e\[3\]\" merged to single register \"shinningblock:U2\|out1_r_e\[3\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 48 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_b_e\[3\] shinningblock:U2\|out1_r_e\[3\] " "Info: Duplicate register \"shinningblock:U2\|out1_b_e\[3\]\" merged to single register \"shinningblock:U2\|out1_r_e\[3\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 49 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_r_o\[3\] shinningblock:U2\|out1_r_e\[3\] " "Info: Duplicate register \"shinningblock:U2\|out1_r_o\[3\]\" merged to single register \"shinningblock:U2\|out1_r_e\[3\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 50 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_g_o\[3\] shinningblock:U2\|out1_r_e\[3\] " "Info: Duplicate register \"shinningblock:U2\|out1_g_o\[3\]\" merged to single register \"shinningblock:U2\|out1_r_e\[3\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 51 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_b_o\[3\] shinningblock:U2\|out1_r_e\[3\] " "Info: Duplicate register \"shinningblock:U2\|out1_b_o\[3\]\" merged to single register \"shinningblock:U2\|out1_r_e\[3\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 52 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_g_e\[2\] shinningblock:U2\|out1_r_e\[2\] " "Info: Duplicate register \"shinningblock:U2\|out1_g_e\[2\]\" merged to single register \"shinningblock:U2\|out1_r_e\[2\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 48 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_b_e\[2\] shinningblock:U2\|out1_r_e\[2\] " "Info: Duplicate register \"shinningblock:U2\|out1_b_e\[2\]\" merged to single register \"shinningblock:U2\|out1_r_e\[2\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 49 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_r_o\[2\] shinningblock:U2\|out1_r_e\[2\] " "Info: Duplicate register \"shinningblock:U2\|out1_r_o\[2\]\" merged to single register \"shinningblock:U2\|out1_r_e\[2\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 50 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_g_o\[2\] shinningblock:U2\|out1_r_e\[2\] " "Info: Duplicate register \"shinningblock:U2\|out1_g_o\[2\]\" merged to single register \"shinningblock:U2\|out1_r_e\[2\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 51 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_b_o\[2\] shinningblock:U2\|out1_r_e\[2\] " "Info: Duplicate register \"shinningblock:U2\|out1_b_o\[2\]\" merged to single register \"shinningblock:U2\|out1_r_e\[2\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 52 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_g_e\[1\] shinningblock:U2\|out1_r_e\[1\] " "Info: Duplicate register \"shinningblock:U2\|out1_g_e\[1\]\" merged to single register \"shinningblock:U2\|out1_r_e\[1\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 48 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_b_e\[1\] shinningblock:U2\|out1_r_e\[1\] " "Info: Duplicate register \"shinningblock:U2\|out1_b_e\[1\]\" merged to single register \"shinningblock:U2\|out1_r_e\[1\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 49 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_r_o\[1\] shinningblock:U2\|out1_r_e\[1\] " "Info: Duplicate register \"shinningblock:U2\|out1_r_o\[1\]\" merged to single register \"shinningblock:U2\|out1_r_e\[1\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 50 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_g_o\[1\] shinningblock:U2\|out1_r_e\[1\] " "Info: Duplicate register \"shinningblock:U2\|out1_g_o\[1\]\" merged to single register \"shinningblock:U2\|out1_r_e\[1\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 51 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_b_o\[1\] shinningblock:U2\|out1_r_e\[1\] " "Info: Duplicate register \"shinningblock:U2\|out1_b_o\[1\]\" merged to single register \"shinningblock:U2\|out1_r_e\[1\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 52 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_g_e\[0\] shinningblock:U2\|out1_r_e\[0\] " "Info: Duplicate register \"shinningblock:U2\|out1_g_e\[0\]\" merged to single register \"shinningblock:U2\|out1_r_e\[0\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 48 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_b_e\[0\] shinningblock:U2\|out1_r_e\[0\] " "Info: Duplicate register \"shinningblock:U2\|out1_b_e\[0\]\" merged to single register \"shinningblock:U2\|out1_r_e\[0\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 49 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_r_o\[0\] shinningblock:U2\|out1_r_e\[0\] " "Info: Duplicate register \"shinningblock:U2\|out1_r_o\[0\]\" merged to single register \"shinningblock:U2\|out1_r_e\[0\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 50 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_g_o\[0\] shinningblock:U2\|out1_r_e\[0\] " "Info: Duplicate register \"shinningblock:U2\|out1_g_o\[0\]\" merged to single register \"shinningblock:U2\|out1_r_e\[0\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 51 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out1_b_o\[0\] shinningblock:U2\|out1_r_e\[0\] " "Info: Duplicate register \"shinningblock:U2\|out1_b_o\[0\]\" merged to single register \"shinningblock:U2\|out1_r_e\[0\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 52 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "shinningblock:U2\|out2_g_e\[7\] shinningblock:U2\|out2_r_e\[7\] " "Info: Duplicate register \"shinningblock:U2\|out2_g_e\[7\]\" merged to single register \"shinningblock:U2\|out2_r_e\[7\]\"" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 54 -1 0 }
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