image.map.qmsg

可以受上位机控制的通过fpga的视频信号发生器程序

{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "q_r_a moving_object.vhd(56) " "Info: (10035) Verilog HDL or VHDL information at moving_object.vhd(56): object \"q_r_a\" declared but not used" {  } { { "moving_object.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/moving_object.vhd" 56 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "q_r_b moving_object.vhd(57) " "Info: (10035) Verilog HDL or VHDL information at moving_object.vhd(57): object \"q_r_b\" declared but not used" {  } { { "moving_object.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/moving_object.vhd" 57 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "q_g_a moving_object.vhd(58) " "Info: (10035) Verilog HDL or VHDL information at moving_object.vhd(58): object \"q_g_a\" declared but not used" {  } { { "moving_object.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/moving_object.vhd" 58 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "q_g_b moving_object.vhd(59) " "Info: (10035) Verilog HDL or VHDL information at moving_object.vhd(59): object \"q_g_b\" declared but not used" {  } { { "moving_object.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/moving_object.vhd" 59 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "q_b_a moving_object.vhd(60) " "Info: (10035) Verilog HDL or VHDL information at moving_object.vhd(60): object \"q_b_a\" declared but not used" {  } { { "moving_object.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/moving_object.vhd" 60 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "q_b_b moving_object.vhd(61) " "Info: (10035) Verilog HDL or VHDL information at moving_object.vhd(61): object \"q_b_b\" declared but not used" {  } { { "moving_object.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/moving_object.vhd" 61 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "ram5.vhd 2 1 " "Info: Using design file ram5.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ram5-SYN " "Info: Found design unit 1: ram5-SYN" {  } { { "ram5.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/ram5.vhd" 54 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 ram5 " "Info: Found entity 1: ram5" {  } { { "ram5.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/ram5.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram5 moving_object:U1\|ram5:u0 " "Info: Elaborating entity \"ram5\" for hierarchy \"moving_object:U1\|ram5:u0\"" {  } { { "moving_object.vhd" "u0" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/moving_object.vhd" 254 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/alt3pram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/alt3pram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt3pram " "Info: Found entity 1: alt3pram" {  } { { "alt3pram.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt3pram.tdf" 97 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt3pram moving_object:U1\|ram5:u0\|alt3pram:alt3pram_component " "Info: Elaborating entity \"alt3pram\" for hierarchy \"moving_object:U1\|ram5:u0\|alt3pram:alt3pram_component\"" {  } { { "ram5.vhd" "alt3pram_component" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/ram5.vhd" 102 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altdpram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altdpram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altdpram " "Info: Found entity 1: altdpram" {  } { { "altdpram.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 164 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altdpram moving_object:U1\|ram5:u0\|alt3pram:alt3pram_component\|altdpram:altdpram_component1 " "Info: Elaborating entity \"altdpram\" for hierarchy \"moving_object:U1\|ram5:u0\|alt3pram:alt3pram_component\|altdpram:altdpram_component1\"" {  } { { "alt3pram.tdf" "altdpram_component1" { Text "c:/altera/quartus50/libraries/megafunctions/alt3pram.tdf" 184 2 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram moving_object:U1\|ram5:u0\|alt3pram:alt3pram_component\|altdpram:altdpram_component1\|altsyncram:ram_block " "Info: Elaborating entity \"altsyncram\" for hierarchy \"moving_object:U1\|ram5:u0\|alt3pram:alt3pram_component\|altdpram:altdpram_component1\|altsyncram:ram_block\"" {  } { { "altdpram.tdf" "ram_block" { Text "c:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 182 4 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_46h1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_46h1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_46h1 " "Info: Found entity 1: altsyncram_46h1" {  } { { "db/altsyncram_46h1.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/altsyncram_46h1.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_46h1 moving_object:U1\|ram5:u0\|alt3pram:alt3pram_component\|altdpram:altdpram_component1\|altsyncram:ram_block\|altsyncram_46h1:auto_generated " "Info: Elaborating entity \"altsyncram_46h1\" for hierarchy \"moving_object:U1\|ram5:u0\|alt3pram:alt3pram_component\|altdpram:altdpram_component1\|altsyncram:ram_block\|altsyncram_46h1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "ram8.vhd 2 1 " "Info: Using design file ram8.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ram8-SYN " "Info: Found design unit 1: ram8-SYN" {  } { { "ram8.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/ram8.vhd" 54 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 ram8 " "Info: Found entity 1: ram8" {  } { { "ram8.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/ram8.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram8 moving_object:U1\|ram8:u1 " "Info: Elaborating entity \"ram8\" for hierarchy \"moving_object:U1\|ram8:u1\"" {  } { { "moving_object.vhd" "u1" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/moving_object.vhd" 267 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt3pram moving_object:U1\|ram8:u1\|alt3pram:alt3pram_component " "Info: Elaborating entity \"alt3pram\" for hierarchy \"moving_object:U1\|ram8:u1\|alt3pram:alt3pram_component\"" {  } { { "ram8.vhd" "alt3pram_component" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/ram8.vhd" 102 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altdpram moving_object:U1\|ram8:u1\|alt3pram:alt3pram_component\|altdpram:altdpram_component1 " "Info: Elaborating entity \"altdpram\" for hierarchy \"moving_object:U1\|ram8:u1\|alt3pram:alt3pram_component\|altdpram:altdpram_component1\"" {  } { { "alt3pram.tdf" "altdpram_component1" { Text "c:/altera/quartus50/libraries/megafunctions/alt3pram.tdf" 184 2 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram moving_object:U1\|ram8:u1\|alt3pram:alt3pram_component\|altdpram:altdpram_component1\|altsyncram:ram_block " "Info: Elaborating entity \"altsyncram\" for hierarchy \"moving_object:U1\|ram8:u1\|alt3pram:alt3pram_component\|altdpram:altdpram_component1\|altsyncram:ram_block\"" {  } { { "altdpram.tdf" "ram_block" { Text "c:/altera/quartus50/libraries/megafunctions/altdpram.tdf" 182 4 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_86h1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_86h1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_86h1 " "Info: Found entity 1: altsyncram_86h1" {  } { { "db/altsyncram_86h1.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/db/altsyncram_86h1.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_86h1 moving_object:U1\|ram8:u1\|alt3pram:alt3pram_component\|altdpram:altdpram_component1\|altsyncram:ram_block\|altsyncram_86h1:auto_generated " "Info: Elaborating entity \"altsyncram_86h1\" for hierarchy \"moving_object:U1\|ram8:u1\|alt3pram:alt3pram_component\|altdpram:altdpram_component1\|altsyncram:ram_block\|altsyncram_86h1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "ram9.vhd 2 1 " "Info: Using design file ram9.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ram9-SYN " "Info: Found design unit 1: ram9-SYN" {  } { { "ram9.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/ram9.vhd" 54 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 ram9 " "Info: Found entity 1: ram9" {  } { { "ram9.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/ram9.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ram9 moving_object:U1\|ram9:u2 " "Info: Elaborating entity \"ram9\" for hierarchy \"moving_object:U1\|ram9:u2\"" {  } { { "moving_object.vhd" "u2" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/moving_object.vhd" 280 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt3pram moving_object:U1\|ram9:u2\|alt3pram:alt3pram_component " "Info: Elaborating entity \"alt3pram\" for hierarchy \"moving_object:U1\|ram9:u2\|alt3pram:alt3pram_component\"" {  } { { "ram9.vhd" "alt3pram_component" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/ram9.vhd" 102 -1 0 } }  } 0}