image.map.qmsg

可以受上位机控制的通过fpga的视频信号发生器程序

{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "out6_r_e image.vhd(69) " "Info: (10035) Verilog HDL or VHDL information at image.vhd(69): object \"out6_r_e\" declared but not used" {  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 69 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "out6_g_e image.vhd(70) " "Info: (10035) Verilog HDL or VHDL information at image.vhd(70): object \"out6_g_e\" declared but not used" {  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 70 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "out6_b_e image.vhd(71) " "Info: (10035) Verilog HDL or VHDL information at image.vhd(71): object \"out6_b_e\" declared but not used" {  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 71 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "out6_r_o image.vhd(72) " "Info: (10035) Verilog HDL or VHDL information at image.vhd(72): object \"out6_r_o\" declared but not used" {  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 72 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "out6_g_o image.vhd(73) " "Info: (10035) Verilog HDL or VHDL information at image.vhd(73): object \"out6_g_o\" declared but not used" {  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 73 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "out6_b_o image.vhd(74) " "Info: (10035) Verilog HDL or VHDL information at image.vhd(74): object \"out6_b_o\" declared but not used" {  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 74 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "out7_r_e image.vhd(75) " "Info: (10035) Verilog HDL or VHDL information at image.vhd(75): object \"out7_r_e\" declared but not used" {  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 75 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "out7_g_e image.vhd(76) " "Info: (10035) Verilog HDL or VHDL information at image.vhd(76): object \"out7_g_e\" declared but not used" {  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 76 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "out7_b_e image.vhd(77) " "Info: (10035) Verilog HDL or VHDL information at image.vhd(77): object \"out7_b_e\" declared but not used" {  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 77 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "out7_r_o image.vhd(78) " "Info: (10035) Verilog HDL or VHDL information at image.vhd(78): object \"out7_r_o\" declared but not used" {  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 78 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "out7_g_o image.vhd(79) " "Info: (10035) Verilog HDL or VHDL information at image.vhd(79): object \"out7_g_o\" declared but not used" {  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 79 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "out7_b_o image.vhd(80) " "Info: (10035) Verilog HDL or VHDL information at image.vhd(80): object \"out7_b_o\" declared but not used" {  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 80 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "out8_r_e image.vhd(81) " "Info: (10035) Verilog HDL or VHDL information at image.vhd(81): object \"out8_r_e\" declared but not used" {  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 81 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "out8_g_e image.vhd(82) " "Info: (10035) Verilog HDL or VHDL information at image.vhd(82): object \"out8_g_e\" declared but not used" {  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 82 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "out8_b_e image.vhd(83) " "Info: (10035) Verilog HDL or VHDL information at image.vhd(83): object \"out8_b_e\" declared but not used" {  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 83 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "out8_r_o image.vhd(84) " "Info: (10035) Verilog HDL or VHDL information at image.vhd(84): object \"out8_r_o\" declared but not used" {  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 84 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "out8_g_o image.vhd(85) " "Info: (10035) Verilog HDL or VHDL information at image.vhd(85): object \"out8_g_o\" declared but not used" {  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 85 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "out8_b_o image.vhd(86) " "Info: (10035) Verilog HDL or VHDL information at image.vhd(86): object \"out8_b_o\" declared but not used" {  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 86 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "expander expander:i2c_expander " "Info: Elaborating entity \"expander\" for hierarchy \"expander:i2c_expander\"" {  } { { "image.vhd" "i2c_expander" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 272 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2cSlave expander:i2c_expander\|i2cSlave:I2Cslavecore_one " "Info: Elaborating entity \"i2cSlave\" for hierarchy \"expander:i2c_expander\|i2cSlave:I2Cslavecore_one\"" {  } { { "expander.tdf" "I2Cslavecore_one" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/expander.tdf" 27 1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "medianFilter expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|medianFilter:sdaMedian " "Info: Elaborating entity \"medianFilter\" for hierarchy \"expander:i2c_expander\|i2cSlave:I2Cslavecore_one\|medianFilter:sdaMedian\"" {  } { { "i2cslave.tdf" "sdaMedian" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/i2cslave.tdf" 156 4 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2cregout expander:i2c_expander\|i2cregout:expander_data " "Info: Elaborating entity \"i2cregout\" for hierarchy \"expander:i2c_expander\|i2cregout:expander_data\"" {  } { { "expander.tdf" "expander_data" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/expander.tdf" 28 1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "importN7bits importN7bits:outdata " "Info: Elaborating entity \"importN7bits\" for hierarchy \"importN7bits:outdata\"" {  } { { "image.vhd" "outdata" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 281 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "moving_object moving_object:U1 " "Info: Elaborating entity \"moving_object\" for hierarchy \"moving_object:U1\"" {  } { { "image.vhd" "U1" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 385 -1 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "tou moving_object.vhd(40) " "Info: (10035) Verilog HDL or VHDL information at moving_object.vhd(40): object \"tou\" declared but not used" {  } { { "moving_object.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/moving_object.vhd" 40 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "bi moving_object.vhd(41) " "Info: (10035) Verilog HDL or VHDL information at moving_object.vhd(41): object \"bi\" declared but not used" {  } { { "moving_object.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/moving_object.vhd" 41 0 0 } }  } 0}