image.map.qmsg

可以受上位机控制的通过fpga的视频信号发生器程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 09 10:28:41 2007 " "Info: Processing started: Thu Aug 09 10:28:41 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off cyclic -c image " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cyclic -c image" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file rom4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rom4-SYN " "Info: Found design unit 1: rom4-SYN" {  } { { "rom4.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/rom4.vhd" 51 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 rom4 " "Info: Found entity 1: rom4" {  } { { "rom4.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/rom4.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "expander.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file expander.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 expander " "Info: Found entity 1: expander" {  } { { "expander.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/expander.tdf" 15 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i2cregin.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file i2cregin.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 i2cregin " "Info: Found entity 1: i2cregin" {  } { { "i2cregin.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/i2cregin.tdf" 12 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i2cregout.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file i2cregout.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 i2cregout " "Info: Found entity 1: i2cregout" {  } { { "i2cregout.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/i2cregout.tdf" 17 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i2cslave.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file i2cslave.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 i2cSlave " "Info: Found entity 1: i2cSlave" {  } { { "i2cslave.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/i2cslave.tdf" 123 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "importN7bits.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file importN7bits.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 importN7bits " "Info: Found entity 1: importN7bits" {  } { { "importN7bits.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/importN7bits.tdf" 22 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "medianfilter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file medianfilter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 medianFilter " "Info: Found entity 1: medianFilter" {  } { { "medianfilter.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/medianfilter.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "posedge.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file posedge.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 posEdge " "Info: Found entity 1: posEdge" {  } { { "posedge.tdf" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/posedge.tdf" 1 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ram1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ram1-SYN " "Info: Found design unit 1: ram1-SYN" {  } { { "ram1.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/ram1.vhd" 56 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 ram1 " "Info: Found entity 1: ram1" {  } { { "ram1.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/ram1.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file rom1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rom1-SYN " "Info: Found design unit 1: rom1-SYN" {  } { { "rom1.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/rom1.vhd" 51 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 rom1 " "Info: Found entity 1: rom1" {  } { { "rom1.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/rom1.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "image.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file image.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 image-rtl " "Info: Found design unit 1: image-rtl" {  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 30 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 image " "Info: Found entity 1: image" {  } { { "image.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/image.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "moving_object.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file moving_object.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 moving_object-rtl " "Info: Found design unit 1: moving_object-rtl" {  } { { "moving_object.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/moving_object.vhd" 38 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 moving_object " "Info: Found entity 1: moving_object" {  } { { "moving_object.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/moving_object.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "moving.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file moving.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 moving-rtl " "Info: Found design unit 1: moving-rtl" {  } { { "moving.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/moving.vhd" 20 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 moving " "Info: Found entity 1: moving" {  } { { "moving.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/moving.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shinning.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file shinning.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 shinning-rtl " "Info: Found design unit 1: shinning-rtl" {  } { { "shinning.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shinning.vhd" 29 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 shinning " "Info: Found entity 1: shinning" {  } { { "shinning.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shinning.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shiningblock.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file shiningblock.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 shinningblock-rtl " "Info: Found design unit 1: shinningblock-rtl" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 39 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 shinningblock " "Info: Found entity 1: shinningblock" {  } { { "shiningblock.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/shiningblock.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rgb.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file rgb.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rgb-rtl " "Info: Found design unit 1: rgb-rtl" {  } { { "rgb.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/rgb.vhd" 26 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 rgb " "Info: Found entity 1: rgb" {  } { { "rgb.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/rgb.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "experiment.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file experiment.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 experiment-rtl " "Info: Found design unit 1: experiment-rtl" {  } { { "experiment.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/experiment.vhd" 31 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 experiment " "Info: Found entity 1: experiment" {  } { { "experiment.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/experiment.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tri_block.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file tri_block.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tri_block-rtl " "Info: Found design unit 1: tri_block-rtl" {  } { { "tri_block.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/tri_block.vhd" 31 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 tri_block " "Info: Found entity 1: tri_block" {  } { { "tri_block.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/tri_block.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "andor.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file andor.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 andor-rtl " "Info: Found design unit 1: andor-rtl" {  } { { "andor.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/andor.vhd" 31 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 andor " "Info: Found entity 1: andor" {  } { { "andor.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/andor.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "catch.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file catch.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 catch-rtl " "Info: Found design unit 1: catch-rtl" {  } { { "catch.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/catch.vhd" 31 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 catch " "Info: Found entity 1: catch" {  } { { "catch.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/catch.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "op3.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file op3.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 op3-rtl " "Info: Found design unit 1: op3-rtl" {  } { { "op3.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/op3.vhd" 32 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 op3 " "Info: Found entity 1: op3" {  } { { "op3.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/op3.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "op1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file op1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 op2-rtl " "Info: Found design unit 1: op2-rtl" {  } { { "op1.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/op1.vhd" 33 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 op2 " "Info: Found entity 1: op2" {  } { { "op1.vhd" "" { Text "D:/CL/Perception/Perception/VHDL-program/VHDL Program-36MHz/op1.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "image " "Info: Elaborating entity \"image\" for the top level hierarchy" {  } {  } 0}