image.hif

可以受上位机控制的通过fpga的视频信号发生器程序

ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
moving_object:U1|rom4:u7
moving_object:U1|rom4:u10
}
# end
# entity
rom5
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
rom5.vhd
1196764992
4
# storage
db|image.(36).cnf
db|image.(36).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
moving_object:U1|rom5:u8
moving_object:U1|rom5:u11
}
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|image.(37).cnf
db|image.(37).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
BIDIR_DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
6
PARAMETER_DEC
USR
NUMWORDS_A
64
PARAMETER_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
8
PARAMETER_DEC
USR
WIDTHAD_B
6
PARAMETER_DEC
USR
NUMWORDS_B
64
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_DEC
USR
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
INIT_FILE
rom5.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_s5t1
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
clock0
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_b0
data_b1
data_b2
data_b3
data_b4
data_b5
data_b6
data_b7
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
wren_a
wren_b
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1118942284
c:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
c:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
c:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
c:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
c:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
c:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
c:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
c:|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
c:|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
}
# hierarchies {
moving_object:U1|rom5:u8|altsyncram:altsyncram_component
moving_object:U1|rom5:u11|altsyncram:altsyncram_component
}
# end
# entity
rom6
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
rom6.vhd
1196765020
4
# storage
db|image.(39).cnf
db|image.(39).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
moving_object:U1|rom6:u9
moving_object:U1|rom6:u12
}
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|image.(40).cnf
db|image.(40).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
BIDIR_DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
6
PARAMETER_DEC
USR
NUMWORDS_A
64
PARAMETER_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
8
PARAMETER_DEC
USR
WIDTHAD_B
6
PARAMETER_DEC
USR
NUMWORDS_B
64
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_DEC
USR
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
INIT_FILE
rom6.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_t5t1
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
clock0
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_b0
data_b1
data_b2
data_b3
data_b4
data_b5
data_b6
data_b7
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
wren_a
wren_b
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1118942284
c:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
c:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
c:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
c:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
c:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
c:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
c:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
c:|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
c:|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
}
# hierarchies {
moving_object:U1|rom6:u9|altsyncram:altsyncram_component
moving_object:U1|rom6:u12|altsyncram:altsyncram_component
}
# end
# entity
ram8
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
ram8.vhd
1196768788
4
# storage
db|image.(42).cnf
db|image.(42).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
moving_object:U1|ram8:u1
}
# end
# entity
alt3pram
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|alt3pram.tdf
1114012440
6
# storage
db|image.(43).cnf
db|image.(43).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH
8
PARAMETER_DEC
USR
WIDTHAD
7
PARAMETER_DEC
USR
NUMWORDS
128
PARAMETER_UNKNOWN
DEF
LPM_FILE
ram8.mif
PARAMETER_UNKNOWN
USR
INDATA_REG
INCLOCK
PARAMETER_UNKNOWN
USR
INDATA_ACLR
OFF
PARAMETER_UNKNOWN
USR
WRITE_REG
INCLOCK
PARAMETER_UNKNOWN
USR
WRITE_ACLR
OFF
PARAMETER_UNKNOWN
USR
RDADDRESS_REG_A
INCLOCK
PARAMETER_UNKNOWN
USR
RDADDRESS_ACLR_A
OFF
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_A
OFF
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
OUTCLOCK
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
OFF
PARAMETER_UNKNOWN
USR
RDADDRESS_REG_B
INCLOCK
PARAMETER_UNKNOWN
USR
RDADDRESS_ACLR_B
OFF
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
OFF
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
OUTCLOCK
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
OFF
PARAMETER_UNKNOWN
USR
USE_EAB
ON
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
}
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
inclock
outclock
qa0
qa1
qa2
qa3
qa4
qa5
qa6
qa7
qb0
qb1
qb2
qb3
qb4
qb5
qb6
qb7
rdaddress_a0
rdaddress_a1
rdaddress_a2
rdaddress_a3
rdaddress_a4
rdaddress_a5
rdaddress_a6
rdaddress_b0
rdaddress_b1
rdaddress_b2
rdaddress_b3
rdaddress_b4
rdaddress_b5
rdaddress_b6
wraddress0
wraddress1
wraddress2
wraddress3
wraddress4
wraddress5
wraddress6
wren
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1118942284
c:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
c:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
moving_object:U1|ram8:u1|alt3pram:alt3pram_component
}
# end
# entity
altdpram
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|altdpram.tdf
1114012440
6
# storage
db|image.(44).cnf
db|image.(44).cnf
# user_parameter {
WIDTH
8
PARAMETER_UNKNOWN
USR
WIDTHAD
7
PARAMETER_UNKNOWN
USR
NUMWORDS
128
PARAMETER_UNKNOWN
USR
FILE
ram8.mif
PARAMETER_UNKNOWN
USR
LPM_FILE
ram8.mif
PARAMETER_UNKNOWN
USR
INDATA_REG
inclock
PARAMETER_UNKNOWN
USR
INDATA_ACLR
OFF
PARAMETER_UNKNOWN
USR
WRADDRESS_REG
inclock
PARAMETER_UNKNOWN
USR
WRADDRESS_ACLR
OFF
PARAMETER_UNKNOWN
USR
WRCONTROL_REG
inclock
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR
OFF
PARAMETER_UNKNOWN
USR
RDADDRESS_REG
inclock
PARAMETER_UNKNOWN
USR
RDADDRESS_ACLR
OFF
PARAMETER_UNKNOWN
USR
RDCONTROL_REG
UNREGISTERED
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR
OFF
PARAMETER_UNKNOWN
USR
OUTDATA_REG
outclock
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR
OFF
PARAMETER_UNKNOWN
USR
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
2048
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
SUPPRESS_MEMORY_CONVERSION_WARNINGS
OFF
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
ENABLE_RAM_BENCHMARKING_MODE
OFF
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
wren
data0
data1
data2
data3
data4
data5
data6
data7
wraddress0
wraddress1
wraddress2
wraddress3
wraddress4
wraddress5
wraddress6
inclock
rdaddress0
rdaddress1
rdaddress2
rdaddress3
rdaddress4
rdaddress5
rdaddress6
outclock
q0
q1
q2
q3
q4
q5
q6
q7
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1118942284
c:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
c:|altera|quartus50|libraries|others|maxplus2|memmodes.inc
1107579370
c:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
c:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
c:|altera|quartus50|libraries|megafunctions|a_hdffe.inc
1107572020
c:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
c:|altera|quartus50|libraries|megafunctions|alt_le_rden_reg.inc
1107572546
c:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
}
# hierarchies {
moving_object:U1|ram8:u1|alt3pram:alt3pram_component|altdpram:altdpram_component1
moving_object:U1|ram8:u1|alt3pram:alt3pram_component|altdpram:altdpram_component2
}