image.hif

可以受上位机控制的通过fpga的视频信号发生器程序

Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
32
1658
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
expander
# case_insensitive
# source_file
expander.tdf
1099377658
6
# storage
db|image.(1).cnf
db|image.(1).cnf
# used_port {
SCL
SDA
clk1
expander_data_out0
expander_data_out1
expander_data_out2
expander_data_out3
expander_data_out4
expander_data_out5
expander_data_out6
expander_data_out7
}
# include_file {
i2cSlave.inc
1099385372
i2cregin.inc
980405938
i2cregout.inc
980405896
}
# hierarchies {
expander:i2c_expander
}
# end
# entity
i2cSlave
# case_insensitive
# source_file
i2cslave.tdf
1099388362
6
# storage
db|image.(2).cnf
db|image.(2).cnf
# user_parameter {
SUBADDRESSBITS
8
PARAMETER_UNKNOWN
USR
NOSUBADDRESS
1
PARAMETER_UNKNOWN
DEF
WAITSTATES
4
PARAMETER_UNKNOWN
DEF
DEBUGMODE
0
PARAMETER_UNKNOWN
DEF
}
# used_port {
clk
slaveaddress1
slaveaddress2
slaveaddress3
slaveaddress4
slaveaddress5
slaveaddress6
slaveaddress7
i2cbusin0
i2cbusin1
i2cbusin2
i2cbusin3
i2cbusin4
i2cbusin5
i2cbusin6
i2cbusin7
i2cbusin8
i2cbusin9
i2cbusin10
i2cbusin11
i2cbusin12
i2cbusin13
i2cbusin14
i2cbusin15
i2cbusin16
i2cbusin17
i2cbusin18
i2cbusin19
i2cbusin20
i2cbusin21
i2cbusin22
i2cbusin23
i2cbusin24
i2cbusin25
i2cbusin26
i2cbusin27
sda
scl
i2cbusout0
i2cbusout1
i2cbusout2
i2cbusout3
i2cbusout4
i2cbusout5
i2cbusout6
i2cbusout7
i2cbusout8
i2cbusout9
i2cbusout10
i2cbusout11
i2cbusout12
i2cbusout13
i2cbusout14
i2cbusout15
i2cbusout16
i2cbusout17
i2cbusout18
i2cbusout19
i2cbusout20
i2cbusout21
i2cbusout22
i2cbusout23
i2cbusout24
i2cbusout25
i2cbusout26
i2cbusout27
}
# include_file {
medianFilter.inc
979895430
}
# hierarchies {
expander:i2c_expander|i2cSlave:I2Cslavecore_one
}
# end
# entity
medianFilter
# case_insensitive
# source_file
medianfilter.tdf
979713150
6
# storage
db|image.(3).cnf
db|image.(3).cnf
# user_parameter {
LENGTH
6
PARAMETER_UNKNOWN
USR
}
# used_port {
clk
in
out
}
# hierarchies {
expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sdaMedian
expander:i2c_expander|i2cSlave:I2Cslavecore_one|medianFilter:sclMedian
}
# end
# entity
i2cregout
# case_insensitive
# source_file
i2cregout.tdf
982644906
6
# storage
db|image.(4).cnf
db|image.(4).cnf
# user_parameter {
SUBADDRESS
0
PARAMETER_UNKNOWN
USR
subaddressbits
8
PARAMETER_UNKNOWN
USR
OUTBITS
8
PARAMETER_UNKNOWN
USR
INITIALVALUE
124
PARAMETER_UNKNOWN
USR
RW
NO
PARAMETER_UNKNOWN
USR
}
# used_port {
i2cbusin0
i2cbusin1
i2cbusin2
i2cbusin3
i2cbusin4
i2cbusin5
i2cbusin6
i2cbusin7
i2cbusin8
i2cbusin9
i2cbusin10
i2cbusin11
i2cbusin12
i2cbusin13
i2cbusin14
i2cbusin15
i2cbusin16
i2cbusin17
i2cbusin18
i2cbusin19
i2cbusin20
i2cbusin21
i2cbusin22
i2cbusin23
i2cbusin24
i2cbusin25
i2cbusin26
i2cbusin27
i2cbusout0
i2cbusout1
i2cbusout2
i2cbusout3
i2cbusout4
i2cbusout5
i2cbusout6
i2cbusout7
i2cbusout8
i2cbusout9
i2cbusout10
i2cbusout11
i2cbusout12
i2cbusout13
i2cbusout14
i2cbusout15
i2cbusout16
i2cbusout17
i2cbusout18
i2cbusout19
i2cbusout20
i2cbusout21
i2cbusout22
i2cbusout23
i2cbusout24
i2cbusout25
i2cbusout26
i2cbusout27
out0
out1
out2
out3
out4
out5
out6
out7
}
# include_file {
posedge.inc
979895808
i2cRegOut.inc
980405896
}
# hierarchies {
expander:i2c_expander|i2cregout:expander_data
}
# end
# entity
importN7bits
# case_insensitive
# source_file
importN7bits.tdf
1168594732
6
# storage
db|image.(5).cnf
db|image.(5).cnf
# used_port {
Xout0
Xout10
Xout11
Xout12
Xout13
Xout14
Xout15
Xout16
Xout17
Xout18
Xout19
Xout1
Xout20
Xout21
Xout22
Xout23
Xout24
Xout25
Xout26
Xout27
Xout28
Xout29
Xout2
Xout30
Xout31
Xout32
Xout33
Xout34
Xout35
Xout36
Xout37
Xout38
Xout39
Xout3
Xout40
Xout41
Xout42
Xout43
Xout44
Xout45
Xout46
Xout47
Xout48
Xout49
Xout4
Xout50
Xout51
Xout52
Xout53
Xout54
Xout55
Xout56
Xout57
Xout58
Xout59
Xout5
Xout60
Xout61
Xout62
Xout63
Xout64
Xout65
Xout66
Xout67
Xout68
Xout69
Xout6
Xout7
Xout8
Xout9
clock
data0
data1
data2
data3
data4
data5
data6
data7
}
# hierarchies {
importN7bits:outdata
}
# end
# entity
ram5
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
ram5.vhd
1168568774
4
# storage
db|image.(7).cnf
db|image.(7).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
moving_object:U1|ram5:u0
}
# end
# entity
alt3pram
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|alt3pram.tdf
1114012440
6
# storage
db|image.(8).cnf
db|image.(8).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH
8
PARAMETER_DEC
USR
WIDTHAD
7
PARAMETER_DEC
USR
NUMWORDS
128
PARAMETER_UNKNOWN
DEF
LPM_FILE
ram5.mif
PARAMETER_UNKNOWN
USR
INDATA_REG
INCLOCK
PARAMETER_UNKNOWN
USR
INDATA_ACLR
OFF
PARAMETER_UNKNOWN
USR
WRITE_REG
INCLOCK
PARAMETER_UNKNOWN
USR
WRITE_ACLR
OFF
PARAMETER_UNKNOWN
USR
RDADDRESS_REG_A
INCLOCK
PARAMETER_UNKNOWN
USR
RDADDRESS_ACLR_A
OFF
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_A
OFF
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
OUTCLOCK
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
OFF
PARAMETER_UNKNOWN
USR
RDADDRESS_REG_B
INCLOCK
PARAMETER_UNKNOWN
USR
RDADDRESS_ACLR_B
OFF
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
OFF
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
OUTCLOCK
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
OFF
PARAMETER_UNKNOWN
USR
USE_EAB
ON
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
}
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
inclock
outclock
qa0
qa1
qa2
qa3
qa4
qa5
qa6
qa7
qb0
qb1
qb2
qb3
qb4
qb5
qb6
qb7
rdaddress_a0
rdaddress_a1
rdaddress_a2
rdaddress_a3
rdaddress_a4
rdaddress_a5
rdaddress_a6
rdaddress_b0
rdaddress_b1
rdaddress_b2
rdaddress_b3
rdaddress_b4
rdaddress_b5
rdaddress_b6
wraddress0
wraddress1
wraddress2
wraddress3
wraddress4
wraddress5
wraddress6
wren
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1118942284
c:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
c:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
moving_object:U1|ram5:u0|alt3pram:alt3pram_component
}
# end
# entity
altdpram
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|altdpram.tdf
1114012440
6
# storage
db|image.(9).cnf
db|image.(9).cnf
# user_parameter {
WIDTH
8
PARAMETER_UNKNOWN
USR
WIDTHAD
7
PARAMETER_UNKNOWN
USR
NUMWORDS
128
PARAMETER_UNKNOWN
USR
FILE
ram5.mif
PARAMETER_UNKNOWN
USR
LPM_FILE
ram5.mif
PARAMETER_UNKNOWN
USR
INDATA_REG
inclock
PARAMETER_UNKNOWN
USR
INDATA_ACLR
OFF
PARAMETER_UNKNOWN
USR
WRADDRESS_REG
inclock
PARAMETER_UNKNOWN
USR
WRADDRESS_ACLR
OFF
PARAMETER_UNKNOWN
USR
WRCONTROL_REG
inclock
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR
OFF
PARAMETER_UNKNOWN
USR
RDADDRESS_REG
inclock
PARAMETER_UNKNOWN
USR
RDADDRESS_ACLR
OFF
PARAMETER_UNKNOWN
USR
RDCONTROL_REG
UNREGISTERED
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR
OFF
PARAMETER_UNKNOWN
USR
OUTDATA_REG
outclock
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR
OFF
PARAMETER_UNKNOWN
USR
USE_EAB
ON
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
2048
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
SUPPRESS_MEMORY_CONVERSION_WARNINGS
OFF
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
ENABLE_RAM_BENCHMARKING_MODE
OFF
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
wren
data0
data1
data2
data3
data4
data5
data6
data7
wraddress0
wraddress1
wraddress2
wraddress3
wraddress4
wraddress5
wraddress6
inclock
rdaddress0
rdaddress1
rdaddress2
rdaddress3
rdaddress4
rdaddress5
rdaddress6
outclock
q0
q1
q2
q3
q4
q5
q6
q7
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1118942284
c:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
c:|altera|quartus50|libraries|others|maxplus2|memmodes.inc
1107579370
c:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
c:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
c:|altera|quartus50|libraries|megafunctions|a_hdffe.inc
1107572020
c:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
c:|altera|quartus50|libraries|megafunctions|alt_le_rden_reg.inc
1107572546
c:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
}
# hierarchies {
moving_object:U1|ram5:u0|alt3pram:alt3pram_component|altdpram:altdpram_component1
moving_object:U1|ram5:u0|alt3pram:alt3pram_component|altdpram:altdpram_component2
}
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|image.(10).cnf
db|image.(10).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_UNKNOWN
USR
WIDTHAD_A
7
PARAMETER_UNKNOWN
USR
NUMWORDS_A
128
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
8
PARAMETER_UNKNOWN
USR
WIDTHAD_B
7
PARAMETER_UNKNOWN
USR
NUMWORDS_B
128
PARAMETER_UNKNOWN
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
USR
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
ram5.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_46h1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_b0
address_b1