image.hier_info

可以受上位机控制的通过fpga的视频信号发生器程序

back[0] => ~NO_FANOUT~
back[1] => ~NO_FANOUT~
back[2] => ~NO_FANOUT~
back[3] => ~NO_FANOUT~
back[4] => ~NO_FANOUT~
back[5] => ~NO_FANOUT~
back[6] => ~NO_FANOUT~
back[7] => ~NO_FANOUT~
front[0] => ~NO_FANOUT~
front[1] => ~NO_FANOUT~
front[2] => ~NO_FANOUT~
front[3] => ~NO_FANOUT~
front[4] => ~NO_FANOUT~
front[5] => ~NO_FANOUT~
front[6] => ~NO_FANOUT~
front[7] => ~NO_FANOUT~
address[0] => rom3:u6.address_a[8]
address[0] => rom6:u12.address_b[1]
address[0] => rom5:u11.address_b[1]
address[0] => rom4:u10.address_b[1]
address[0] => rom6:u12.address_a[1]
address[0] => rom5:u11.address_a[1]
address[0] => rom4:u10.address_a[1]
address[0] => rom6:u9.address_b[1]
address[0] => rom5:u8.address_b[1]
address[0] => rom4:u7.address_b[1]
address[0] => rom6:u9.address_a[1]
address[0] => rom5:u8.address_a[1]
address[0] => rom4:u7.address_a[1]
address[0] => rom3:u6.address_b[8]
address[0] => rom2:u5.address_b[8]
address[0] => rom1:u4.address_b[8]
address[0] => rom2:u5.address_a[8]
address[0] => rom1:u4.address_a[8]
address[1] => rom3:u6.address_a[9]
address[1] => rom6:u12.address_b[2]
address[1] => rom5:u11.address_b[2]
address[1] => rom4:u10.address_b[2]
address[1] => rom6:u12.address_a[2]
address[1] => rom5:u11.address_a[2]
address[1] => rom4:u10.address_a[2]
address[1] => rom6:u9.address_b[2]
address[1] => rom5:u8.address_b[2]
address[1] => rom4:u7.address_b[2]
address[1] => rom6:u9.address_a[2]
address[1] => rom5:u8.address_a[2]
address[1] => rom4:u7.address_a[2]
address[1] => rom3:u6.address_b[9]
address[1] => rom2:u5.address_b[9]
address[1] => rom1:u4.address_b[9]
address[1] => rom2:u5.address_a[9]
address[1] => rom1:u4.address_a[9]
address[2] => rom3:u6.address_a[10]
address[2] => rom6:u12.address_b[3]
address[2] => rom5:u11.address_b[3]
address[2] => rom4:u10.address_b[3]
address[2] => rom6:u12.address_a[3]
address[2] => rom5:u11.address_a[3]
address[2] => rom4:u10.address_a[3]
address[2] => rom6:u9.address_b[3]
address[2] => rom5:u8.address_b[3]
address[2] => rom4:u7.address_b[3]
address[2] => rom6:u9.address_a[3]
address[2] => rom5:u8.address_a[3]
address[2] => rom4:u7.address_a[3]
address[2] => rom3:u6.address_b[10]
address[2] => rom2:u5.address_b[10]
address[2] => rom1:u4.address_b[10]
address[2] => rom2:u5.address_a[10]
address[2] => rom1:u4.address_a[10]
address[3] => rom3:u6.address_a[11]
address[3] => rom6:u12.address_b[4]
address[3] => rom5:u11.address_b[4]
address[3] => rom4:u10.address_b[4]
address[3] => rom6:u12.address_a[4]
address[3] => rom5:u11.address_a[4]
address[3] => rom4:u10.address_a[4]
address[3] => rom6:u9.address_b[4]
address[3] => rom5:u8.address_b[4]
address[3] => rom4:u7.address_b[4]
address[3] => rom6:u9.address_a[4]
address[3] => rom5:u8.address_a[4]
address[3] => rom4:u7.address_a[4]
address[3] => rom3:u6.address_b[11]
address[3] => rom2:u5.address_b[11]
address[3] => rom1:u4.address_b[11]
address[3] => rom2:u5.address_a[11]
address[3] => rom1:u4.address_a[11]
address[4] => rom3:u6.address_a[12]
address[4] => rom6:u12.address_b[5]
address[4] => rom5:u11.address_b[5]
address[4] => rom4:u10.address_b[5]
address[4] => rom6:u12.address_a[5]
address[4] => rom5:u11.address_a[5]
address[4] => rom4:u10.address_a[5]
address[4] => rom6:u9.address_b[5]
address[4] => rom5:u8.address_b[5]
address[4] => rom4:u7.address_b[5]
address[4] => rom6:u9.address_a[5]
address[4] => rom5:u8.address_a[5]
address[4] => rom4:u7.address_a[5]
address[4] => rom3:u6.address_b[12]
address[4] => rom2:u5.address_b[12]
address[4] => rom1:u4.address_b[12]
address[4] => rom2:u5.address_a[12]
address[4] => rom1:u4.address_a[12]
address[5] => ~NO_FANOUT~
address[6] => ~NO_FANOUT~
address[7] => ~NO_FANOUT~
data_r[0] => add~28.IN64
data_r[1] => add~28.IN63
data_r[2] => add~28.IN62
data_r[3] => add~28.IN61
data_r[4] => add~28.IN60
data_r[5] => add~28.IN59
data_r[6] => add~28.IN58
data_r[7] => add~28.IN57
data_g[0] => ~NO_FANOUT~
data_g[1] => ~NO_FANOUT~
data_g[2] => ~NO_FANOUT~
data_g[3] => ~NO_FANOUT~
data_g[4] => ~NO_FANOUT~
data_g[5] => ~NO_FANOUT~
data_g[6] => ~NO_FANOUT~
data_g[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
out_r_e[0] <= out_r_e[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_r_e[1] <= out_r_e[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_r_e[2] <= out_r_e[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_r_e[3] <= out_r_e[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_r_e[4] <= out_r_e[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_r_e[5] <= out_r_e[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_r_e[6] <= out_r_e[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_r_e[7] <= out_r_e[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_g_e[0] <= out_g_e[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_g_e[1] <= out_g_e[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_g_e[2] <= out_g_e[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_g_e[3] <= out_g_e[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_g_e[4] <= out_g_e[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_g_e[5] <= out_g_e[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_g_e[6] <= out_g_e[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_g_e[7] <= out_g_e[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_b_e[0] <= out_b_e[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_b_e[1] <= out_b_e[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_b_e[2] <= out_b_e[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_b_e[3] <= out_b_e[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_b_e[4] <= out_b_e[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_b_e[5] <= out_b_e[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_b_e[6] <= out_b_e[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_b_e[7] <= out_b_e[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_r_o[0] <= out_r_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_r_o[1] <= out_r_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_r_o[2] <= out_r_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_r_o[3] <= out_r_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_r_o[4] <= out_r_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_r_o[5] <= out_r_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_r_o[6] <= out_r_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_r_o[7] <= out_r_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_g_o[0] <= out_g_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_g_o[1] <= out_g_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_g_o[2] <= out_g_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_g_o[3] <= out_g_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_g_o[4] <= out_g_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_g_o[5] <= out_g_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_g_o[6] <= out_g_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_g_o[7] <= out_g_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_b_o[0] <= out_b_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_b_o[1] <= out_b_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_b_o[2] <= out_b_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_b_o[3] <= out_b_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_b_o[4] <= out_b_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_b_o[5] <= out_b_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_b_o[6] <= out_b_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out_b_o[7] <= out_b_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|image|moving_object:U1|ram5:u0
data[0] => alt3pram:alt3pram_component.data[0]
data[1] => alt3pram:alt3pram_component.data[1]
data[2] => alt3pram:alt3pram_component.data[2]
data[3] => alt3pram:alt3pram_component.data[3]
data[4] => alt3pram:alt3pram_component.data[4]
data[5] => alt3pram:alt3pram_component.data[5]
data[6] => alt3pram:alt3pram_component.data[6]
data[7] => alt3pram:alt3pram_component.data[7]
wraddress[0] => alt3pram:alt3pram_component.wraddress[0]
wraddress[1] => alt3pram:alt3pram_component.wraddress[1]
wraddress[2] => alt3pram:alt3pram_component.wraddress[2]
wraddress[3] => alt3pram:alt3pram_component.wraddress[3]
wraddress[4] => alt3pram:alt3pram_component.wraddress[4]
wraddress[5] => alt3pram:alt3pram_component.wraddress[5]
wraddress[6] => alt3pram:alt3pram_component.wraddress[6]
rdaddress_a[0] => alt3pram:alt3pram_component.rdaddress_a[0]
rdaddress_a[1] => alt3pram:alt3pram_component.rdaddress_a[1]
rdaddress_a[2] => alt3pram:alt3pram_component.rdaddress_a[2]
rdaddress_a[3] => alt3pram:alt3pram_component.rdaddress_a[3]
rdaddress_a[4] => alt3pram:alt3pram_component.rdaddress_a[4]
rdaddress_a[5] => alt3pram:alt3pram_component.rdaddress_a[5]
rdaddress_a[6] => alt3pram:alt3pram_component.rdaddress_a[6]
rdaddress_b[0] => alt3pram:alt3pram_component.rdaddress_b[0]
rdaddress_b[1] => alt3pram:alt3pram_component.rdaddress_b[1]
rdaddress_b[2] => alt3pram:alt3pram_component.rdaddress_b[2]
rdaddress_b[3] => alt3pram:alt3pram_component.rdaddress_b[3]
rdaddress_b[4] => alt3pram:alt3pram_component.rdaddress_b[4]
rdaddress_b[5] => alt3pram:alt3pram_component.rdaddress_b[5]
rdaddress_b[6] => alt3pram:alt3pram_component.rdaddress_b[6]
wren => alt3pram:alt3pram_component.wren
clock => alt3pram:alt3pram_component.inclock
clock => alt3pram:alt3pram_component.outclock
qa[0] <= alt3pram:alt3pram_component.qa[0]
qa[1] <= alt3pram:alt3pram_component.qa[1]
qa[2] <= alt3pram:alt3pram_component.qa[2]
qa[3] <= alt3pram:alt3pram_component.qa[3]
qa[4] <= alt3pram:alt3pram_component.qa[4]
qa[5] <= alt3pram:alt3pram_component.qa[5]
qa[6] <= alt3pram:alt3pram_component.qa[6]
qa[7] <= alt3pram:alt3pram_component.qa[7]
qb[0] <= alt3pram:alt3pram_component.qb[0]
qb[1] <= alt3pram:alt3pram_component.qb[1]
qb[2] <= alt3pram:alt3pram_component.qb[2]
qb[3] <= alt3pram:alt3pram_component.qb[3]
qb[4] <= alt3pram:alt3pram_component.qb[4]
qb[5] <= alt3pram:alt3pram_component.qb[5]
qb[6] <= alt3pram:alt3pram_component.qb[6]
qb[7] <= alt3pram:alt3pram_component.qb[7]


|image|moving_object:U1|ram5:u0|alt3pram:alt3pram_component
wren => altdpram:altdpram_component1.wren
wren => altdpram:altdpram_component2.wren
data[0] => altdpram:altdpram_component1.data[0]
data[0] => altdpram:altdpram_component2.data[0]
data[1] => altdpram:altdpram_component1.data[1]
data[1] => altdpram:altdpram_component2.data[1]
data[2] => altdpram:altdpram_component1.data[2]
data[2] => altdpram:altdpram_component2.data[2]
data[3] => altdpram:altdpram_component1.data[3]
data[3] => altdpram:altdpram_component2.data[3]
data[4] => altdpram:altdpram_component1.data[4]
data[4] => altdpram:altdpram_component2.data[4]
data[5] => altdpram:altdpram_component1.data[5]
data[5] => altdpram:altdpram_component2.data[5]
data[6] => altdpram:altdpram_component1.data[6]
data[6] => altdpram:altdpram_component2.data[6]
data[7] => altdpram:altdpram_component1.data[7]
data[7] => altdpram:altdpram_component2.data[7]
wraddress[0] => altdpram:altdpram_component1.wraddress[0]
wraddress[0] => altdpram:altdpram_component2.wraddress[0]
wraddress[1] => altdpram:altdpram_component1.wraddress[1]
wraddress[1] => altdpram:altdpram_component2.wraddress[1]
wraddress[2] => altdpram:altdpram_component1.wraddress[2]
wraddress[2] => altdpram:altdpram_component2.wraddress[2]
wraddress[3] => altdpram:altdpram_component1.wraddress[3]
wraddress[3] => altdpram:altdpram_component2.wraddress[3]
wraddress[4] => altdpram:altdpram_component1.wraddress[4]
wraddress[4] => altdpram:altdpram_component2.wraddress[4]
wraddress[5] => altdpram:altdpram_component1.wraddress[5]
wraddress[5] => altdpram:altdpram_component2.wraddress[5]
wraddress[6] => altdpram:altdpram_component1.wraddress[6]
wraddress[6] => altdpram:altdpram_component2.wraddress[6]
inclock => altdpram:altdpram_component1.inclock
inclock => altdpram:altdpram_component2.inclock
inclocken => ~NO_FANOUT~
outclock => altdpram:altdpram_component1.outclock
outclock => altdpram:altdpram_component2.outclock
outclocken => ~NO_FANOUT~
aclr => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
rdaddress_a[0] => altdpram:altdpram_component1.rdaddress[0]
rdaddress_a[1] => altdpram:altdpram_component1.rdaddress[1]
rdaddress_a[2] => altdpram:altdpram_component1.rdaddress[2]
rdaddress_a[3] => altdpram:altdpram_component1.rdaddress[3]
rdaddress_a[4] => altdpram:altdpram_component1.rdaddress[4]
rdaddress_a[5] => altdpram:altdpram_component1.rdaddress[5]
rdaddress_a[6] => altdpram:altdpram_component1.rdaddress[6]
rdaddress_b[0] => altdpram:altdpram_component2.rdaddress[0]
rdaddress_b[1] => altdpram:altdpram_component2.rdaddress[1]
rdaddress_b[2] => altdpram:altdpram_component2.rdaddress[2]
rdaddress_b[3] => altdpram:altdpram_component2.rdaddress[3]
rdaddress_b[4] => altdpram:altdpram_component2.rdaddress[4]
rdaddress_b[5] => altdpram:altdpram_component2.rdaddress[5]
rdaddress_b[6] => altdpram:altdpram_component2.rdaddress[6]
qa[0] <= altdpram:altdpram_component1.q[0]
qa[1] <= altdpram:altdpram_component1.q[1]
qa[2] <= altdpram:altdpram_component1.q[2]
qa[3] <= altdpram:altdpram_component1.q[3]
qa[4] <= altdpram:altdpram_component1.q[4]
qa[5] <= altdpram:altdpram_component1.q[5]
qa[6] <= altdpram:altdpram_component1.q[6]
qa[7] <= altdpram:altdpram_component1.q[7]
qb[0] <= altdpram:altdpram_component2.q[0]
qb[1] <= altdpram:altdpram_component2.q[1]
qb[2] <= altdpram:altdpram_component2.q[2]
qb[3] <= altdpram:altdpram_component2.q[3]
qb[4] <= altdpram:altdpram_component2.q[4]
qb[5] <= altdpram:altdpram_component2.q[5]
qb[6] <= altdpram:altdpram_component2.q[6]
qb[7] <= altdpram:altdpram_component2.q[7]


|image|moving_object:U1|ram5:u0|alt3pram:alt3pram_component|altdpram:altdpram_component1
wren => altsyncram:ram_block.wren_a
data[0] => altsyncram:ram_block.data_a[0]
data[1] => altsyncram:ram_block.data_a[1]
data[2] => altsyncram:ram_block.data_a[2]
data[3] => altsyncram:ram_block.data_a[3]
data[4] => altsyncram:ram_block.data_a[4]
data[5] => altsyncram:ram_block.data_a[5]
data[6] => altsyncram:ram_block.data_a[6]
data[7] => altsyncram:ram_block.data_a[7]
wraddress[0] => altsyncram:ram_block.address_a[0]
wraddress[1] => altsyncram:ram_block.address_a[1]
wraddress[2] => altsyncram:ram_block.address_a[2]
wraddress[3] => altsyncram:ram_block.address_a[3]
wraddress[4] => altsyncram:ram_block.address_a[4]
wraddress[5] => altsyncram:ram_block.address_a[5]
wraddress[6] => altsyncram:ram_block.address_a[6]
inclock => altsyncram:ram_block.clock0
inclocken => ~NO_FANOUT~
rden => ~NO_FANOUT~
rdaddress[0] => altsyncram:ram_block.address_b[0]
rdaddress[1] => altsyncram:ram_block.address_b[1]
rdaddress[2] => altsyncram:ram_block.address_b[2]
rdaddress[3] => altsyncram:ram_block.address_b[3]
rdaddress[4] => altsyncram:ram_block.address_b[4]
rdaddress[5] => altsyncram:ram_block.address_b[5]
rdaddress[6] => altsyncram:ram_block.address_b[6]
outclock => altsyncram:ram_block.clock1
outclocken => ~NO_FANOUT~
aclr => ~NO_FANOUT~
q[0] <= altsyncram:ram_block.q_b[0]
q[1] <= altsyncram:ram_block.q_b[1]
q[2] <= altsyncram:ram_block.q_b[2]
q[3] <= altsyncram:ram_block.q_b[3]
q[4] <= altsyncram:ram_block.q_b[4]
q[5] <= altsyncram:ram_block.q_b[5]
q[6] <= altsyncram:ram_block.q_b[6]
q[7] <= altsyncram:ram_block.q_b[7]


|image|moving_object:U1|ram5:u0|alt3pram:alt3pram_component|altdpram:altdpram_component1|altsyncram:ram_block
wren_a => altsyncram_46h1:auto_generated.wren_a
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_46h1:auto_generated.data_a[0]
data_a[1] => altsyncram_46h1:auto_generated.data_a[1]
data_a[2] => altsyncram_46h1:auto_generated.data_a[2]
data_a[3] => altsyncram_46h1:auto_generated.data_a[3]
data_a[4] => altsyncram_46h1:auto_generated.data_a[4]
data_a[5] => altsyncram_46h1:auto_generated.data_a[5]
data_a[6] => altsyncram_46h1:auto_generated.data_a[6]
data_a[7] => altsyncram_46h1:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
address_a[0] => altsyncram_46h1:auto_generated.address_a[0]
address_a[1] => altsyncram_46h1:auto_generated.address_a[1]
address_a[2] => altsyncram_46h1:auto_generated.address_a[2]
address_a[3] => altsyncram_46h1:auto_generated.address_a[3]
address_a[4] => altsyncram_46h1:auto_generated.address_a[4]
address_a[5] => altsyncram_46h1:auto_generated.address_a[5]
address_a[6] => altsyncram_46h1:auto_generated.address_a[6]
address_b[0] => altsyncram_46h1:auto_generated.address_b[0]