moving_object.vhd

可以受上位机控制的通过fpga的视频信号发生器程序

LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY moving_object IS PORT
( clk    : IN std_logic;
  vcount : IN std_logic_vector(11 DOWNTO 0);
  hcount : IN std_logic_vector(10 DOWNTO 0);
  clken_fcount: IN std_logic;
  pattern : IN std_logic_vector(3  DOWNTO 0);
  distance:IN std_logic_vector(3  DOWNTO 0);
  wren    : IN std_logic;
  mode    : in std_logic;
  time      : IN  std_logic_vector(3 DOWNTO 0);
  back      : IN  std_logic_vector(7 DOWNTO 0);
  front     : IN  std_logic_vector(7 DOWNTO 0);
  address   : IN  std_logic_vector(7 DOWNTO 0);
  data_r    : IN  std_logic_vector(7 DOWNTO 0);
  data_g    : IN  std_logic_vector(7 DOWNTO 0);
  data_b    : IN  std_logic_vector(7 DOWNTO 0);
  out_r_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_g_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_b_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_r_o   : OUT std_logic_vector(7 DOWNTO 0);
  out_g_o   : OUT std_logic_vector(7 DOWNTO 0);
  out_b_o   : OUT std_logic_vector(7 DOWNTO 0)
);
CONSTANT HAC:integer:=684;   -- horizontal active pixels 1448*1151
CONSTANT HSY:integer:=16;     -- horizontal sync width (negative polarity)
CONSTANT HBP:integer:=40;     -- horizontal back porch
CONSTANT VAC:integer:=768;    -- vertical active pixels
CONSTANT VSY:integer:=5;      -- vertical sync width (negative polarity)
CONSTANT VBP:integer:=15;     -- vertical back porch


END moving_object;
ARCHITECTURE rtl OF moving_object IS
	SIGNAL nn,speed,dist,count,countmax: integer;
	SIGNAL color,tou : std_logic_vector(1 DOWNTO 0);
	signal bi: std_logic;
	SIGNAL address_a: STD_LOGIC_VECTOR(10 DOWNTO 0);
	SIGNAL address_b: STD_LOGIC_VECTOR(10 DOWNTO 0);
	SIGNAL address1_a: STD_LOGIC_VECTOR(10 DOWNTO 0);
	SIGNAL address1_b: STD_LOGIC_VECTOR(10 DOWNTO 0);
	
	signal ada:STD_LOGIC_VECTOR(7 DOWNTO 0);
	signal adb:STD_LOGIC_VECTOR(7 DOWNTO 0);
	signal count1:STD_LOGIC_VECTOR(6 DOWNTO 0);
	signal ad1a:STD_LOGIC_VECTOR(6 DOWNTO 0);
	signal ad1b:STD_LOGIC_VECTOR(6 DOWNTO 0);
	signal wdata:STD_LOGIC_VECTOR(7 DOWNTO 0);
	signal ada1:STD_LOGIC_VECTOR(12 DOWNTO 0);
	signal adb1:STD_LOGIC_VECTOR(12 DOWNTO 0);
	SIGNAL barcolor:STD_LOGIC_VECTOR(7 DOWNTO 0);
	SIGNAL q_r_a:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL q_r_b:STD_LOGIC_VECTOR(7 DOWNTO 0);
	SIGNAL q_g_a:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL q_g_b:STD_LOGIC_VECTOR(7 DOWNTO 0);
	SIGNAL q_b_a:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL q_b_b:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL q1_a:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL q1_b:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL r_a:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL r_b:STD_LOGIC_VECTOR(7 DOWNTO 0);
	SIGNAL g_a:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL g_b:STD_LOGIC_VECTOR(7 DOWNTO 0);
	SIGNAL b_a:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL b_b:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL r_a_1:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL r_b_1:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL g_a_1:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL g_b_1:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL b_a_1:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL b_b_1:STD_LOGIC_VECTOR(7 DOWNTO 0);
    signal K1:STD_LOGIC_VECTOR(5 DOWNTO 0);
    signal K2:STD_LOGIC_VECTOR(5 DOWNTO 0);
    signal K3:STD_LOGIC_VECTOR(5 DOWNTO 0);
    signal K4:STD_LOGIC_VECTOR(5 DOWNTO 0);
    SIGNAL r_a_2:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL r_b_2:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL g_a_2:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL g_b_2:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL b_a_2:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL b_b_2:STD_LOGIC_VECTOR(7 DOWNTO 0);
    signal wdata1:STD_LOGIC_VECTOR(7 DOWNTO 0);
    signal wdata2:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL q2_a:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL q2_b:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL q3_a:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL q3_b:STD_LOGIC_VECTOR(7 DOWNTO 0);

COMPONENT ram1 IS
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wraddress		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rdaddress_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rdaddress_b		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wren		: IN STD_LOGIC  := '1';
		clock		: IN STD_LOGIC ;
		rden_a		: IN STD_LOGIC  := '1';
		rden_b		: IN STD_LOGIC  := '1';
		qa		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		qb		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END COMPONENT;


component ram5
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wraddress		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
		rdaddress_a		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
		rdaddress_b		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
		wren		: IN STD_LOGIC  := '1';
		clock		: IN STD_LOGIC ;
		qa		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		qb		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
end component;

component ram8
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wraddress		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
		rdaddress_a		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
		rdaddress_b		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
		wren		: IN STD_LOGIC  := '1';
		clock		: IN STD_LOGIC ;
		qa		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		qb		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
end component;

component ram9
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wraddress		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
		rdaddress_a		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
		rdaddress_b		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
		wren		: IN STD_LOGIC  := '1';
		clock		: IN STD_LOGIC ;
		qa		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		qb		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
end component;


component ram6
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wraddress		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rdaddress_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rdaddress_b		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wren		: IN STD_LOGIC  := '1';
		rden_a		: IN STD_LOGIC  := '1';
		rden_b		: IN STD_LOGIC  := '1';
		clock		: IN STD_LOGIC ;
		qa		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		qb		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
end component;

component ram7
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wraddress		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rdaddress_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rdaddress_b		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wren		: IN STD_LOGIC  := '1';
		rden_a		: IN STD_LOGIC  := '1';
		rden_b		: IN STD_LOGIC  := '1';
		clock		: IN STD_LOGIC ;
		qa		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		qb		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
end component;


component rom1
	PORT
	(
		clock		: IN STD_LOGIC ;
		address_a		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
		address_b		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		q_b		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
end component;

component rom2
	PORT
	(
		clock		: IN STD_LOGIC ;
		address_a		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
		address_b		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		q_b		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
end component;

component rom3
	PORT
	(
		clock		: IN STD_LOGIC ;
		address_a		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
		address_b		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		q_b		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
end component;

component rom4
	PORT
	(
		clock		: IN STD_LOGIC ;
		address_a		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		address_b		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		q_b		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
end component;

component rom5
	PORT
	(
		clock		: IN STD_LOGIC ;
		address_a		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		address_b		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		q_b		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
end component;

component rom6
	PORT
	(
		clock		: IN STD_LOGIC ;
		address_a		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		address_b		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		q_b		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
end component;

BEGIN

u0: ram5
port map
(  
data=>wdata,
wraddress=>count1,
rdaddress_a=>ad1a,
rdaddress_b=>ad1b,
wren=>'1',
clock=>clk,
qa=>q1_a,
qb=>q1_b
);

u1: ram8
port map
(  
data=>wdata1,
wraddress=>count1,
rdaddress_a=>ad1a,
rdaddress_b=>ad1b,
wren=>'1',
clock=>clk,
qa=>q2_a,
qb=>q2_b
);

u2: ram9
port map
(  
data=>wdata2,
wraddress=>count1,
rdaddress_a=>ad1a,
rdaddress_b=>ad1b,
wren=>'1',
clock=>clk,
qa=>q3_a,
qb=>q3_b
);
--u1: ram1
--port map
--(  
--data=>data_r,
--wraddress=>address,
--rdaddress_a=>ada,
--rdaddress_b=>adb,
--wren=>wren,
--rden_a=>not wren,		
--rden_b=>not wren,		
--clock=>clk,
--qa=>q_r_a,
--qb=>q_r_b
--);

--u2: ram6
--port map
--(  
--data=>data_g,
--wraddress=>address,
--rdaddress_a=>ada,
--rdaddress_b=>adb,
--wren=>wren,
--rden_a=>not wren,		
--rden_b=>not wren,		
--clock=>clk,
--qa=>q_g_a,
--qb=>q_g_b
--);

--u3: ram7
--port map
--(  
--data=>data_b,
--wraddress=>address,
--rdaddress_a=>ada,
--rdaddress_b=>adb,
--wren=>wren,
--rden_a=>not wren,		-
--rden_b=>not wren,		
--clock=>clk,
--qa=>q_b_a,
--qb=>q_b_b
--);

u4: rom1
port map
(  
address_a=>ada1,
address_b=>adb1,
clock=>clk,
q_a=>r_a,
q_b=>r_b
);

u5: rom2
port map
(  
address_a=>ada1,
address_b=>adb1,
clock=>clk,
q_a=>g_a,
q_b=>g_b
);

u6: rom3
port map
(  
address_a=>ada1,
address_b=>adb1,
clock=>clk,
q_a=>b_a,
q_b=>b_b
);

u7: rom4
port map
(  
address_a=>K1,
address_b=>K2,
clock=>clk,
q_a=>r_a_1,
q_b=>r_b_1
);

u8: rom5
port map
(  
address_a=>K1,
address_b=>K2,
clock=>clk,
q_a=>g_a_1,
q_b=>g_b_1
);

u9: rom6
port map
(  
address_a=>K1,
address_b=>K2,
clock=>clk,
q_a=>b_a_1,
q_b=>b_b_1
);

u10: rom4
port map
(  
address_a=>K3,
address_b=>K4,
clock=>clk,
q_a=>r_a_2,
q_b=>r_b_2
);

u11: rom5
port map
(  
address_a=>K3,
address_b=>K4,
clock=>clk,
q_a=>g_a_2,
q_b=>g_b_2
);

u12: rom6
port map
(  
address_a=>K3,
address_b=>K4,
clock=>clk,
q_a=>b_a_2,
q_b=>b_b_2
);

PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
count1<=count1+1;
end if;
end process;

process(clk)
BEGIN
IF clk'event AND clk='1' THEN
if count1<100 then
wdata<=r_a_1;
wdata1<=g_a_1;
wdata2<=b_a_1;
else
wdata<=r_a_2;
wdata1<=g_a_2;
wdata2<=b_a_2;
end if;
end if;
end process;


PROCESS(distance)
BEGIN
CASE distance IS
	WHEN  "0000"=>dist<=25;
	WHEN  "0001"=>dist<=50;
	WHEN  "0010"=>dist<=75;
    WHEN  "0011"=>dist<=100;
    WHEN  "0100"=>dist<=125;
    WHEN  "0101"=>dist<=150;
    WHEN  "0110"=>dist<=175;
    WHEN  "0111"=>dist<=200;
    WHEN  "1000"=>dist<=225;
    WHEN  "1001"=>dist<=250;
    When others =>dist<=0;
END CASE;
END PROCESS;

barcolor<="00100000";

PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
if hcount>=292+HBP+HSY and hcount<392+HBP+HSY
then
address_a<=hcount+hcount-HBP-HSY-HBP-HSY-584;
address_b<=hcount+hcount-HBP-HSY-HBP-HSY-583;
else
address_a<="00000000000";
address_b<="00000000000";
end if;
end if;
end process;


ada<=address_a(7 downto 0);
adb<=address_b(7 downto 0);
ada1<=address(4 downto 0)&address_a(7 downto 0);
adb1<=address(4 downto 0)&address_b(7 downto 0);
K1<=address(4 downto 0)&"1";
K2<=address(4 downto 0)&"1";
K3<=address(4 downto 0)&"0";
K4<=address(4 downto 0)&"0";
speed<=conv_integer(data_r);
countmax<=conv_integer(time)*30;
address1_a<=(hcount+hcount-HBP-HSY-HBP-HSY-nn);
address1_b<=(hcount+hcount-HBP-HSY-HBP-HSY-nn+1);

Process(clk,address1_a)
BEGIN
IF clk'event AND clk='1' THEN
if  address1_a<100
then ad1a<=address1_a(6 downto 0);
else 
ad1a<="1111111";
end if;
end if;
end process;

Process(clk,address1_b)
BEGIN
IF clk'event AND clk='1' THEN
if  address1_b<100
then ad1b<=address1_b(6 downto 0);
else 
ad1b<="1111111";
end if;
end if;
end process;


PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
IF vcount>=284+VBP+VSY-25 AND vcount<384+VBP+VSY-25  
then
if  (hcount>=262-dist+HBP+HSY and  hcount<267-dist+HBP+HSY) or
         (hcount>=417+dist+HBP+HSY and  hcount<422+dist+HBP+HSY)
then color<="11";
elsif hcount>=267-dist+HBP+HSY AND hcount<(417+dist+HBP+HSY) then
color<="01";
else
color<="00";
end if;

elsif (vcount>=384+VBP+VSY-25 AND vcount<384+VBP+VSY+25) or
       vcount>=484+VBP+VSY+25  or vcount<284+VBP+VSY-25
     
then if  (hcount>=262-dist+HBP+HSY and  hcount<267-dist+HBP+HSY) or
         (hcount>=417+dist+HBP+HSY and  hcount<422+dist+HBP+HSY)
then color<="11";
else color<="00";
end if;

elsif vcount>=384+VBP+VSY+25 AND vcount<484+VBP+VSY+25 
then if hcount>=267-dist+HBP+HSY AND hcount<(417+dist+HBP+HSY) 
then color<="10";
elsif (hcount>=262-dist+HBP+HSY and  hcount<267-dist+HBP+HSY) or
         (hcount>=417+dist+HBP+HSY and  hcount<422+dist+HBP+HSY)
then
color<="11";
else color<="00";
end if;
else color<="00";
END IF;
END IF;
END PROCESS;

PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
IF clken_fcount='1' THEN
IF nn>=834+dist+dist THEN 
if count=countmax
then
nn<=434-dist-dist;
count<=0;
else 
count<=count+1;
nn<=834+dist+dist;
end if;
ELSE
nn<=(nn+speed);
END IF;
END IF;
END IF;
END PROCESS;



PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
if mode='0' then
IF color="01" THEN
out_r_e<=r_a;
out_g_e<=g_a;
out_b_e<=b_a;
out_r_o<=r_b;
out_g_o<=g_b;
out_b_o<=b_b;
ELSIF color="10" THEN
out_r_e<=q1_a;
out_g_e<=q2_a;
out_b_e<=q3_a;
out_r_o<=q1_b;
out_g_o<=q2_b;
out_b_o<=q3_b;
ELSIF color="11" THEN
out_r_e<=barcolor;
out_g_e<=barcolor;
out_b_e<=barcolor;
out_r_o<=barcolor;
out_g_o<=barcolor;
out_b_o<=barcolor;

else
out_r_e<=r_a_2;
out_g_e<=g_a_2;
out_b_e<=b_a_2;
out_r_o<=r_b_2;
out_g_o<=g_b_2;
out_b_o<=b_b_2;
end if;

elsIF color="10" THEN
out_r_e<=r_a;
out_g_e<=g_a;
out_b_e<=b_a;
out_r_o<=r_b;
out_g_o<=g_b;
out_b_o<=b_b;
ELSIF color="01" THEN
out_r_e<=q1_a;
out_g_e<=q2_a;
out_b_e<=q3_a;
out_r_o<=q1_b;
out_g_o<=q2_b;
out_b_o<=q3_b;
ELSIF color="11" THEN
out_r_e<=barcolor;
out_g_e<=barcolor;
out_b_e<=barcolor;
out_r_o<=barcolor;
out_g_o<=barcolor;
out_b_o<=barcolor;
else
out_r_e<=r_a_2;
out_g_e<=g_a_2;
out_b_e<=b_a_2;
out_r_o<=r_b_2;
out_g_o<=g_b_2;
out_b_o<=b_b_2;

END IF;
END IF;
END PROCESS;


END rtl;