op2.vhd

可以受上位机控制的通过fpga的视频信号发生器程序

LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;


ENTITY op2 IS PORT
( clk    : IN std_logic;
  vcount : IN std_logic_vector(11 DOWNTO 0);
  hcount : IN std_logic_vector(10 DOWNTO 0);
  clken_fcount: IN std_logic;
  pattern : IN std_logic_vector(3  DOWNTO 0);
  distance: IN std_logic_vector(3  DOWNTO 0);
  wren    : IN std_logic;
  mode    : IN std_logic;
  sel       : IN  std_logic_vector(7 DOWNTO 0);
  address   : IN  std_logic_vector(7 DOWNTO 0);
  date      : IN  std_logic_vector(7 DOWNTO 0);
  out_r_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_g_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_b_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_r_o   : OUT std_logic_vector(7 DOWNTO 0);
  out_g_o   : OUT std_logic_vector(7 DOWNTO 0);
  out_b_o   : OUT std_logic_vector(7 DOWNTO 0)
);
CONSTANT HAC:integer:=640;   -- horizontal active pixels 1448*1151
CONSTANT HSY:integer:=20;     -- horizontal sync width (negative polarity)
CONSTANT HBP:integer:=20;     -- horizontal back porch
CONSTANT VAC:integer:=1024;    -- vertical active pixels
CONSTANT VSY:integer:=25;      -- vertical sync width (negative polarity)
CONSTANT VBP:integer:=25;     -- vertical back porch

END op2;
ARCHITECTURE rtl OF op2 IS
	SIGNAL speed,dist,cmax,h_dis: integer;
	SIGNAL nn:integer;
	signal hz: std_logic;
	SIGNAL color : std_logic_vector(1 DOWNTO 0);
	SIGNAL address_a: STD_LOGIC_VECTOR(10 DOWNTO 0);
	SIGNAL address_b: STD_LOGIC_VECTOR(10 DOWNTO 0);
	SIGNAL address1_a: STD_LOGIC_VECTOR(10 DOWNTO 0);
	SIGNAL address1_b: STD_LOGIC_VECTOR(10 DOWNTO 0);
	signal count: std_logic_vector(9 downto 0);
	signal idate:STD_LOGIC_VECTOR(7 DOWNTO 0);
	signal ada:STD_LOGIC_VECTOR(8 DOWNTO 0);
	signal adb:STD_LOGIC_VECTOR(8 DOWNTO 0);
	signal ada1:STD_LOGIC_VECTOR(7 DOWNTO 0);
	signal adb1:STD_LOGIC_VECTOR(7 DOWNTO 0);
	SIGNAL q_a:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL q_b:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL q1_a:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL q1_b:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL front:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL back:STD_LOGIC_VECTOR(7 DOWNTO 0);
COMPONENT ram3 IS
PORT
	(
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wraddress		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
		rdaddress_a		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
		rdaddress_b		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
		wren		: IN STD_LOGIC  := '1';
		clock		: IN STD_LOGIC ;
		qa		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		qb		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END COMPONENT;

COMPONENT ram4 IS
PORT
	(
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wraddress		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rdaddress_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rdaddress_b		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wren		: IN STD_LOGIC  := '1';
		clock		: IN STD_LOGIC ;
		qa		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		qb		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END COMPONENT;


BEGIN
u1: ram3
port map
(  
data=>idate,
wraddress=>count(8 downto 0),
rdaddress_a=>ada,
rdaddress_b=>adb,
wren=>'1',
clock=>clk,
qa=>q_a,
qb=>q_b
);

u2: ram4
port map
(  
data=>date,
wraddress=>address,
rdaddress_a=>ada1,
rdaddress_b=>adb1,
wren=>wren,
clock=>clk,
qa=>q1_a,
qb=>q1_b
);

PROCESS(clk,hz)
BEGIN
IF clk'event AND clk='1' THEN
if hz='1' then count<="0000000000";
else count<=count+1;
end if;
end if;
end process;
hz<='1' when count=cmax else '0';
cmax<=250+dist+dist+dist+dist+dist;

process(clk)
BEGIN
IF clk'event AND clk='1' THEN
if count<50 or (count>=50+dist and count<100+dist) 
or(count>=100+dist+dist and count<150+dist+dist) 
or (count>=150+dist+dist+dist and count<200+dist+dist+dist) 
or (count>=200+dist+dist+dist+dist and count<250+dist+dist+dist+dist) 
then
idate<=front;
else idate<=back;
end if;
end if;
end process;

PROCESS(distance)
BEGIN
CASE distance IS
	WHEN  "0000"=>dist<=42;
	              h_dis<=15;
	WHEN  "0001"=>dist<=36;
	              h_dis<=30;
	WHEN  "0010"=>dist<=30;
	              h_dis<=45;
	WHEN  "0011"=>dist<=24;
	              h_dis<=60;
    WHEN  "0100"=>dist<=18;
                  h_dis<=75;
    WHEN  "0101"=>dist<=12;
                  h_dis<=90;
    WHEN  "0110"=>dist<=6;
                  h_dis<=105;
    When others =>dist<=48;
                  h_dis<=0;
END CASE;
END PROCESS;


PROCESS(sel)
BEGIN
CASE sel IS
    WHEN  "00000000"=>back<="00000000";
                  front<="00110010";
	WHEN  "00000001"=>back<="00000000";
	              front<="01001110";
	WHEN  "00000010"=>back<="00000000";
	              front<="01101111";
    WHEN  "00000011"=>back<="00000000";
                  front<="10010110";
    WHEN  "00000100"=>back<="00000000";
                  front<="11000100";
    WHEN  "00000101"=>back<="00000000";
                  front<="11111111";
    
    WHEN  "00000110"=>back<="00110010";
                  front<="01001110";
    WHEN  "00000111"=>back<="00110010";
                  front<="01101111";
    WHEN  "00001000"=>back<="00110010";
                  front<="10010110";
    WHEN  "00001001"=>back<="00110010";
                  front<="11000100";
    WHEN  "00001010"=>back<="00110010";
                  front<="11111111";

    WHEN  "00001011"=>back<="01001110";
                  front<="01101111";
    WHEN  "00001100"=>back<="01001110";
                  front<="10010110"; 
    WHEN  "00001101"=>back<="01001110";
                  front<="11000100";
    WHEN  "00001110"=>back<="01001110";
                  front<="11111111";
     
WHEN  "00001111"=>back<="01101111";
                  front<="10010110";
 WHEN  "00010000"=>back<="01101111";
                  front<="11000100";
 WHEN  "00010001"=>back<="01101111";
                  front<="11111111";

 WHEN  "00010010"=>back<="10010110";
                  front<="11000100";
 WHEN  "00010011"=>back<="10010110";
                  front<="11111111";

WHEN  "00010100"=>back<="11000100";
                  front<="11111111";


    When others=>back<="00000000";
                 front<="00000000";
END CASE;
END PROCESS;


ada<=address_a(8 downto 0);
adb<=address_b(8 downto 0);
speed<=conv_integer(pattern);

process(clk,mode)
BEGIN
IF clk'event AND clk='1' THEN
if
hcount+hcount-HBP-HSY-HBP-HSY>=nn and hcount+hcount-HBP-HSY-HBP-HSY<nn+495-h_dis-h_dis
then
address_a<=hcount+hcount-HBP-HSY-HBP-HSY-nn;
address_b<=hcount+hcount-HBP-HSY-HBP-HSY-nn+1;
else 
address_a<="00000111000";
address_b<="00000111000";
end if;
end if;	
end process;

ada1<=address1_a(7 downto 0);
adb1<=address1_b(7 downto 0);

process(clk)
BEGIN
IF clk'event AND clk='1' THEN
if hcount+hcount-HBP-HSY-HBP-HSY-390>=0 and hcount+hcount-HBP-HSY-HBP-HSY-390<100
then
address1_a<=hcount+hcount-HBP-HSY-HBP-HSY-390;
address1_b<=hcount+hcount-HBP-HSY-HBP-HSY-389;
elsif hcount+hcount-HBP-HSY-HBP-HSY-390>=100 and hcount+hcount-HBP-HSY-HBP-HSY-390<200
then
address1_a<=hcount+hcount-HBP-HSY-HBP-HSY-490;
address1_b<=hcount+hcount-HBP-HSY-HBP-HSY-489;
elsif hcount+hcount-HBP-HSY-HBP-HSY-390>=200 and hcount+hcount-HBP-HSY-HBP-HSY-390<300
then
address1_a<=hcount+hcount-HBP-HSY-HBP-HSY-590;
address1_b<=hcount+hcount-HBP-HSY-HBP-HSY-589;
elsif hcount+hcount-HBP-HSY-HBP-HSY-390>=300 and hcount+hcount-HBP-HSY-HBP-HSY-390<400
then
address1_a<=hcount+hcount-HBP-HSY-HBP-HSY-690;
address1_b<=hcount+hcount-HBP-HSY-HBP-HSY-689;
elsif hcount+hcount-HBP-HSY-HBP-HSY-390>=400 and hcount+hcount-HBP-HSY-HBP-HSY-390<500
then
address1_a<=hcount+hcount-HBP-HSY-HBP-HSY-790;
address1_b<=hcount+hcount-HBP-HSY-HBP-HSY-789;
else 
address1_a<="00000000000";
address1_b<="00000000000";
end if;
end if;
end process;



PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
IF vcount>=187+VBP+VSY AND vcount<487+VBP+VSY and hcount>=195+HBP+HSY and hcount<HBP+HSY+445
then
color<="01";
ELSIF vcount>=537+VBP+VSY AND vcount<837+VBP+VSY 
then
color<="10";
else
color<="00";
END IF;
END IF;
END PROCESS;

PROCESS(clk,mode)
BEGIN
IF clk'event AND clk='1' THEN
IF clken_fcount='1' THEN
if mode='0'
then
IF nn>=(490-h_dis-h_dis) THEN 
nn<=0;
ELSE
nn<=(nn+speed+speed);
END IF;
end if;
elsif nn>=HAC
then nn<=0;
else
nn<=(nn+speed+speed);
END IF;
END IF;
END PROCESS;


PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
IF color="01" THEN
out_r_e<=q1_a;
out_g_e<=q1_a;
out_b_e<=q1_a;
out_r_o<=q1_b;
out_g_o<=q1_b;
out_b_o<=q1_b;
ELSIF color="10" THEN
out_r_e<=q_a;
out_g_e<=q_a;
out_b_e<=q_a;
out_r_o<=q_b;
out_g_o<=q_b;
out_b_o<=q_b;
ELSE
out_r_e<=back;
out_g_e<=back;
out_b_e<=back;
out_r_o<=back;
out_g_o<=back;
out_b_o<=back;
END IF;
END IF;
END PROCESS;

END rtl;