image.vhd

可以受上位机控制的通过fpga的视频信号发生器程序

hs <='1' when hcountreg >=HSY AND hcountreg < HTOT
ELSE '0';
hz <= '1' when hcountreg = HTOT ELSE '0';
END BLOCK hcount;

--判断行脉冲上升延，产生列起始信号
vstart : BLOCK
SIGNAL inputa : std_logic;
SIGNAL inputb : std_logic;
BEGIN
PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
inputb <= inputa;
inputa <= NOT hs;
END IF;
END PROCESS;
clken_vcount <= NOT inputb AND inputa;
END BLOCK vstart;

--产生列同步和de
vcount : BLOCK
SIGNAL vz : std_logic;
BEGIN
PROCESS (clk,vz)
BEGIN
IF(vz='1')THEN
vcountreg <= (OTHERS => '0');
ELSIF clk'event AND clk = '1' THEN
IF clken_vcount = '1' THEN
vcountreg <= vcountreg +1;
END IF;
END IF;
END PROCESS;
vb <= '1' when vcountreg >=VBP+VSY AND vcountreg < VBP+VSY+VAC
ELSE '0';
vs <='1' when vcountreg >=VSY AND vcountreg < VTOT
ELSE '0';
vz <= '1' when vcountreg = VTOT ELSE '0';
END BLOCK vcount;

--判断列脉冲上升延，产生帧起始信号
fstart : BLOCK
SIGNAL inputc : std_logic;
SIGNAL inputd : std_logic;
BEGIN
PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
inputd <= inputc;
inputc <= NOT vs;
END IF;
END PROCESS;
clken_fcount <= NOT inputd AND inputc;
END BLOCK fstart;

U1 : moving_object
	PORT MAP
	(
		 clk  =>  clk,
		 vcount => vcountreg,
		 hcount => hcountreg,
		 clken_fcount => clken_fcount,
		 pattern => time1,
		 distance=> time2,
		 wren    => startin,
		 front   => level3,
		 back    => size&pos,
		 data_r  =>level2,
		 data_g  =>fulldata(61 downto 54),
		 data_b  =>fulldata(69 downto 62),
		 mode=>mode,
		 time=>time3,
		 address=>level1,
		 out_r_e  => out1_r_e,
		 out_g_e  => out1_g_e,
		 out_b_e  => out1_b_e,
		 out_r_o  => out1_r_o,
		 out_g_o  => out1_g_o,
		 out_b_o  => out1_b_o
	);


U2: shinningblock
  PORT MAP
(
		 clk    =>  clk,
		 vcount => vcountreg,
		 hcount => hcountreg,
		 clken_fcount => clken_fcount,
		 mode     => mode,
		 startin  => startin,
		 outsel=>outsel,
		 refresh => refresh,
		 time1    => time1,
		 time2    => time2,
		 time3    => time3,
		 level1   => level1,
		 level2   => level2,
		 level3    => level3,
		 size     => size,
		 pos      => pos,
		 trigger  => trigger,
		 out_r_e  => out2_r_e,
		 out_g_e  => out2_g_e,
		 out_b_e  => out2_b_e,
		 out_r_o  => out2_r_o,
		 out_g_o  => out2_g_o,
		 out_b_o  => out2_b_o
);

U3: shinning
   PORT MAP
(
		 clk  =>  clk,
		 vcount => vcountreg,
		 hcount => hcountreg,
		 clken_fcount => clken_fcount,
		 time1    => time1,
		 level1   => level1,
		 refresh=> refresh,
		 out_r_e  => out3_r_e,
		 out_g_e  => out3_g_e,
		 out_b_e  => out3_b_e,
		 out_r_o  => out3_r_o,
		 out_g_o  => out3_g_o,
		 out_b_o  => out3_b_o
		
	);
u4: rgb
   PORT MAP
(        clk   =>  clk,
         vcount => vcountreg,
		 hcount => hcountreg,
		 sel    => mode,
		 level1 => level1,
         out_r_e  => out5_r_e,
		 out_g_e  => out5_g_e,
		 out_b_e  => out5_b_e,
		 out_r_o  => out5_r_o,
		 out_g_o  => out5_g_o,
		 out_b_o  => out5_b_o
		);
--U5 : experiment
--	PORT MAP
--	(
--		 clk  =>  clk,
--		 vcount => vcountreg,
--		 hcount => hcountreg,
--		 clken_fcount => clken_fcount,
--		 pattern => time1,
--		 distance=> time2,
--		 distance1 => time3,
--		 level1=>level1,
--		 level2=>level2,
--		 level3=>level3,
--		selection=>selection,
--		 out_r_e  => out6_r_e,
--		 out_g_e  => out6_g_e,
--		 out_b_e  => out6_b_e,
--		 out_r_o  => out6_r_o,
--		 out_g_o  => out6_g_o,
---		 out_b_o  => out6_b_o
--	);

--U6 : op3
--	PORT MAP
--	(
--		 clk  =>  clk,
--		 vcount => vcountreg,
--		 hcount => hcountreg,
--		 clken_fcount => clken_fcount,
--		 pattern => time1,
--		 distance=> time2,
--		 wren    => startin,
--		 mode    =>mode,
--		 sel     => level3,
--		 data=>level2,
--		 address=>level1,
--		 out_r_e  => out7_r_e,
--		 out_g_e  => out7_g_e,
--		 out_b_e  => out7_b_e,
--		 out_r_o  => out7_r_o,
--		 out_g_o  => out7_g_o,
--		 out_b_o  => out7_b_o
--	);

--U7 : op2
--	PORT MAP
--	(
--		 clk  =>  clk,
---		 vcount => vcountreg,
--		 hcount => hcountreg,
--		 clken_fcount => clken_fcount,
--		 pattern => time1,
--		 distance=> time2,
--		 wren    => startin,
--		 sel     => level3,
--		 data=>level2,
--		 address=>level1,
--		 out_r_e  => out8_r_e,
--		 out_g_e  => out8_g_e,
--		 out_b_e  => out8_b_e,
--		 out_r_o  => out8_r_o,
--		 out_g_o  => out8_g_o,
--		 out_b_o  => out8_b_o
--	);
	

process(refresh)
begin
CASE refresh IS
WHEN "01"=>HTOT<=850;
           VTOT<=852;
WHEN "10"=>HTOT<=764;
           VTOT<=790;
WHEN OTHERS =>HTOT<=764;
           VTOT<=790;
END CASE;
END PROCESS;

process(clk)
begin
if clk'event AND clk = '1' THEN
CASE rgb_sel IS
WHEN "00"=> out_r_e <= out4_r_e;
			out_b_e <= out4_b_e;
			out_g_e <= out4_g_e;
			out_r_o <= out4_r_o;
			out_b_o <= out4_b_o;
			out_g_o <= out4_g_o;
           
WHEN "01"=> out_r_e <= out4_r_e;
			out_b_e <= "00000000";
			out_g_e <= "00000000";
			out_r_o <= out4_r_o;
			out_b_o <= "00000000";
			out_g_o <= "00000000";

WHEN "10"=> out_r_e <= "00000000";
			out_b_e <= out4_b_e;
			out_g_e <= "00000000";
			out_r_o <= "00000000";
			out_b_o <= out4_b_o;
			out_g_o <= "00000000";

WHEN "11"=> out_r_e <= "00000000";
			out_b_e <= "00000000";
			out_g_e <= out4_g_e;
			out_r_o <= "00000000";
			out_b_o <= "00000000";
			out_g_o <= out4_g_o;
END CASE;
END IF;
END PROCESS;

PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
CASE chose IS
	WHEN "001"=>
		out4_r_e <= out2_r_e;
		out4_b_e <= out2_b_e;
		out4_g_e <= out2_g_e;
		out4_r_o <= out2_r_o;
		out4_b_o <= out2_b_o;
		out4_g_o <= out2_g_o;
	WHEN "010"=>
		out4_r_e <= out1_r_e;
		out4_b_e <= out1_b_e;
		out4_g_e <= out1_g_e;
		out4_r_o <= out1_r_o;
		out4_b_o <= out1_b_o;
		out4_g_o <= out1_g_o;
	WHEN "011" =>
		out4_r_e <= out3_r_e;
		out4_b_e <= out3_b_e;
		out4_g_e <= out3_g_e;
		out4_r_o <= out3_r_o;
		out4_b_o <= out3_b_o;
		out4_g_o <= out3_g_o;
	WHEN "100" =>
	    out4_r_e <= out5_r_e;
		out4_b_e <= out5_b_e;
		out4_g_e <= out5_g_e;
		out4_r_o <= out5_r_o;
		out4_b_o <= out5_b_o;
		out4_g_o <= out5_g_o;
--	WHEN "101" =>
--	    out4_r_e <= out6_r_e;
--		out4_b_e <= out6_b_e;
--		out4_g_e <= out6_g_e;
--		out4_r_o <= out6_r_o;
--		out4_b_o <= out6_b_o;
--		out4_g_o <= out6_g_o;
--	when"110"=>
--	    out4_r_e <= out8_r_e;
--		out4_b_e <= out8_b_e;
--		out4_g_e <= out8_g_e;
--		out4_r_o <= out8_r_o;
--		out4_b_o <= out8_b_o;
--		out4_g_o <= out8_g_o;
--	when "111"=>
--	    out4_r_e <= out7_r_e;
--		out4_b_e <= out7_b_e;
--		out4_g_e <= out7_g_e;
--		out4_r_o <= out7_r_o;
--	    out4_b_o <= out7_b_o;
	--	out4_g_o <= out7_g_o;
	when others=>
	    out4_r_e <= "00000000";
		out4_b_e <= "00000000";
		out4_g_e <= "00000000";
		out4_r_o <= "00000000";
		out4_b_o <= "00000000";
		out4_g_o <= "00000000";
END CASE;
END IF;
END PROCESS;
pixs_out<='1';
clk_out<=clk;
de_out <=hb AND vb;
hs_out <=hs;
vs_out <=vs;
END rtl;