image.vhd

可以受上位机控制的通过fpga的视频信号发生器程序

LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY image IS
PORT(   sda     : INOUT std_logic;
 		scl     : INOUT std_logic;
        clk     : IN std_logic;
        clk_out : OUT std_logic;
		hs_out  : OUT std_logic;
		de_out  : BUFFER std_logic;
		vs_out  : OUT std_logic;
		pixs_out:OUT std_logic;
		trigger : OUT std_logic;
		out_r_e   : OUT std_logic_vector(7 DOWNTO 0);
		out_g_e   : OUT std_logic_vector(7 DOWNTO 0);
		out_b_e   : OUT std_logic_vector(7 DOWNTO 0);
		out_r_o   : OUT std_logic_vector(7 DOWNTO 0);
		out_g_o   : OUT std_logic_vector(7 DOWNTO 0);
		out_b_o   : OUT std_logic_vector(7 DOWNTO 0));

CONSTANT HAC:integer:=684;   -- horizontal active pixels 1448*1151
CONSTANT HSY:integer:=16;     -- horizontal sync width (negative polarity)
CONSTANT HBP:integer:=40;     -- horizontal back porch
CONSTANT VAC:integer:=768;    -- vertical active pixels
CONSTANT VSY:integer:=5;      -- vertical sync width (negative polarity)
CONSTANT VBP:integer:=15;     -- vertical back porch
end;

ARCHITECTURE rtl OF image IS
SIGNAL VTOT :integer;
SIGNAL HTOT :integer;
SIGNAL hb : std_logic;
SIGNAL hs : std_logic;
SIGNAL vb : std_logic;
SIGNAL vs : std_logic;
SIGNAL clken_vcount : std_logic;
SIGNAL clken_fcount : std_logic;
SIGNAL out1_r_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out1_g_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out1_b_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out1_r_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out1_g_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out1_b_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out2_r_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out2_g_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out2_b_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out2_r_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out2_g_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out2_b_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out3_r_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out3_g_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out3_b_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out3_r_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out3_g_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out3_b_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out4_r_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out4_g_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out4_b_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out4_r_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out4_g_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out4_b_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out5_r_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out5_g_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out5_b_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out5_r_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out5_g_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out5_b_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out6_r_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out6_g_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out6_b_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out6_r_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out6_g_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out6_b_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out7_r_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out7_g_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out7_b_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out7_r_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out7_g_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out7_b_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out8_r_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out8_g_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out8_b_e    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out8_r_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out8_g_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL out8_b_o    :   std_logic_vector(7 DOWNTO 0);
SIGNAL vcountreg :  std_logic_vector(11 DOWNTO 0);
SIGNAL hcountreg :  std_logic_vector(10 DOWNTO 0);
SIGNAL expander_interface:std_logic_vector(7 DOWNTO 0);
SIGNAL fulldata: std_logic_vector(69 DOWNTO 0);
SIGNAL mode    : std_logic;
SIGNAL startin : std_logic;
SIGNAL time1  :  std_logic_vector(3  DOWNTO 0);
SIGNAL time2  :  std_logic_vector(3  DOWNTO 0);
SIGNAL time3  :  std_logic_vector(3  DOWNTO 0);
SIGNAL level1 :  std_logic_vector(7  DOWNTO 0);
SIGNAL level2 :  std_logic_vector(7  DOWNTO 0);
SIGNAl level3 :  std_logic_vector(7  DOWNTO 0);
SIGNAL size   :  std_logic_vector(3  DOWNTO 0);
SIGNAL rgb_sel:  std_logic_vector(1  DOWNTO 0);
SIGNAL chose  :  std_logic_vector(2  DOWNTO 0);
SIGNAL refresh:  std_logic_vector(1  DOWNTO 0);
signal pos    : std_logic_vector(3  DOWNTO 0);
signal outsel : std_logic;
SIGNAL selection  :  std_logic_vector(1  DOWNTO 0);


	
COMPONENT moving_object IS PORT
		( clk    : IN std_logic;
		  vcount : IN std_logic_vector(11 DOWNTO 0);
		  hcount : IN std_logic_vector(10 DOWNTO 0);
		  clken_fcount: IN std_logic;
		  pattern   : IN  std_logic_vector(3 DOWNTO 0);
		  distance  : IN  std_logic_vector(3 DOWNTO 0);
		  wren      : IN std_logic;
		  mode      : in std_logic;
		  time      : IN  std_logic_vector(3 DOWNTO 0);
		  back      : IN  std_logic_vector(7 DOWNTO 0);
		  front     : IN  std_logic_vector(7 DOWNTO 0);
		  address   : IN  std_logic_vector(7 DOWNTO 0);
		  data_r    : IN  std_logic_vector(7 DOWNTO 0);
		  data_g    : IN  std_logic_vector(7 DOWNTO 0);
		  data_b    : IN  std_logic_vector(7 DOWNTO 0);
		  out_r_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_g_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_b_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_r_o   : OUT std_logic_vector(7 DOWNTO 0);
		  out_g_o   : OUT std_logic_vector(7 DOWNTO 0);
		  out_b_o   : OUT std_logic_vector(7 DOWNTO 0))
;
END COMPONENT;

component op2 IS PORT
( clk    : IN std_logic;
  vcount : IN std_logic_vector(11 DOWNTO 0);
  hcount : IN std_logic_vector(10 DOWNTO 0);
  clken_fcount: IN std_logic;
  pattern : IN std_logic_vector(3  DOWNTO 0);
  wren    : IN std_logic;
  distance: IN std_logic_vector(3  DOWNTO 0);
  sel       : IN  std_logic_vector(7 DOWNTO 0);
  address   : IN  std_logic_vector(7 DOWNTO 0);
  data      : IN  std_logic_vector(7 DOWNTO 0);
  out_r_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_g_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_b_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_r_o   : OUT std_logic_vector(7 DOWNTO 0);
  out_g_o   : OUT std_logic_vector(7 DOWNTO 0);
  out_b_o   : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;

COMPONENT op3 IS PORT
( clk    : IN std_logic;
  vcount : IN std_logic_vector(11 DOWNTO 0);
  hcount : IN std_logic_vector(10 DOWNTO 0);
  clken_fcount: IN std_logic;
  pattern: IN std_logic_vector(3  DOWNTO 0);
  distance:IN std_logic_vector(3  DOWNTO 0);
  wren    : IN std_logic;
  mode    : IN std_logic;
  sel       : IN  std_logic_vector(7 DOWNTO 0);
  address   : IN  std_logic_vector(7 DOWNTO 0);
  data      : IN  std_logic_vector(7 DOWNTO 0);
  out_r_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_g_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_b_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_r_o   : OUT std_logic_vector(7 DOWNTO 0);
  out_g_o   : OUT std_logic_vector(7 DOWNTO 0);
  out_b_o   : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;


COMPONENT shinning IS PORT
		( clk    : IN std_logic;
		  vcount : IN std_logic_vector(11 DOWNTO 0);
		  hcount : IN std_logic_vector(10 DOWNTO 0);
		  clken_fcount: IN std_logic;
		  time1  : IN std_logic_vector(3  DOWNTO 0);
          level1 : IN std_logic_vector(7  DOWNTO 0);
		  refresh: IN std_logic_vector(1 DOWNTO 0);
		  out_r_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_g_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_b_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_r_o   : OUT std_logic_vector(7 DOWNTO 0);
		  out_g_o   : OUT std_logic_vector(7 DOWNTO 0);
		  out_b_o   : OUT std_logic_vector(7 DOWNTO 0));
END COMPONENT;

COMPONENT shinningblock IS PORT
		( clk    : IN std_logic;
		  vcount : IN std_logic_vector(11 DOWNTO 0);
		  hcount : IN std_logic_vector(10 DOWNTO 0);
		  clken_fcount: IN std_logic;
		  mode   : IN std_logic;
		  startin: IN std_logic;
		  outsel : IN std_logic;
		  refresh: IN std_logic_vector(1  DOWNTO 0);
		  time1  : IN std_logic_vector(3  DOWNTO 0);
		  time2  : IN std_logic_vector(3  DOWNTO 0);
		  time3  : IN std_logic_vector(3  DOWNTO 0);
		  level1 : IN std_logic_vector(7  DOWNTO 0);
		  level2 : IN std_logic_vector(7  DOWNTO 0);
		  level3 : IN std_logic_vector(7  DOWNTO 0);
		  size   : IN std_logic_vector(3  DOWNTO 0);
		  pos    : IN std_logic_vector(3  DOWNTO 0);
		  trigger : OUT std_logic;
		  out_r_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_g_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_b_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_r_o   : OUT std_logic_vector(7 DOWNTO 0);
		  out_g_o   : OUT std_logic_vector(7 DOWNTO 0);
		  out_b_o   : OUT std_logic_vector(7 DOWNTO 0));
END COMPONENT;

COMPONENT rgb IS PORT
( clk    : IN std_logic;
  vcount : IN std_logic_vector(11 DOWNTO 0);
  hcount : IN std_logic_vector(10 DOWNTO 0);
  sel    : IN std_logic;
  level1 : IN std_logic_vector(7 DOWNTO 0);
  out_r_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_g_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_b_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_r_o   : OUT std_logic_vector(7 DOWNTO 0);
  out_g_o   : OUT std_logic_vector(7 DOWNTO 0);
  out_b_o   : OUT std_logic_vector(7 DOWNTO 0));
END COMPONENT;
COMPONENT experiment IS PORT
		( clk    : IN std_logic;
		  vcount : IN std_logic_vector(11 DOWNTO 0);
		  hcount : IN std_logic_vector(10 DOWNTO 0);
		  clken_fcount: IN std_logic;
		  pattern   : IN  std_logic_vector(3 DOWNTO 0);
		  distance  : IN  std_logic_vector(3 DOWNTO 0);
		  distance1  : IN  std_logic_vector(3 DOWNTO 0);
		  level1   : IN  std_logic_vector(7 DOWNTO 0);
		  level2   : IN  std_logic_vector(7 DOWNTO 0);
		  level3      : IN  std_logic_vector(7 DOWNTO 0);
		  out_r_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_g_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_b_e   : OUT std_logic_vector(7 DOWNTO 0);
		  out_r_o   : OUT std_logic_vector(7 DOWNTO 0);
		  out_g_o   : OUT std_logic_vector(7 DOWNTO 0);
		  out_b_o   : OUT std_logic_vector(7 DOWNTO 0);
		selection   : IN  std_logic_vector(1 DOWNTO 0))
;
END COMPONENT;


COMPONENT expander 
PORT   (
		SCL					:	in std_logic; 
		SDA					:	in std_logic;
		expander_data_out	:	out std_logic_vector(7 downto 0);
		clk1				:	in std_logic
		);
	end component;

component importN7bits
port   (
		clock			:	in std_logic; 
		data			:	in std_logic_vector(7 downto 0);
		Xout			:	out std_logic_vector(69 downto 0)
		);

 end component;

BEGIN
i2c_expander		:	expander
	PORT MAP (
		SCL			=> scl,
		SDA			=> sda,	
		expander_data_out  	=> expander_interface,
		clk1			=> clk
	
	);

outdata: importN7bits
PORT MAP(
     	clock   =>  clk,
        data   => expander_interface,
        Xout   => fulldata
);



process(clk)
begin
if clk'event AND clk = '1' THEN
if clken_fcount='1' then
startin<=fulldata(0);
mode<=fulldata(1);
outsel<=fulldata(2);
time1<=fulldata(6 downto 3);
time2<=fulldata(10 downto 7);
time3<=fulldata(14 downto 11);
size<=fulldata(18 downto 15);
level1<=fulldata(26 downto 19);
level2<=fulldata(34 downto 27);
rgb_sel<=fulldata(36 downto 35);
chose<=fulldata(39 downto 37);
refresh<=fulldata(41 downto 40);
level3<=fulldata(49 downto 42);
pos<=fulldata(53 downto 50);

selection<=fulldata(55 downto 54);

end if;
end if;
end process;

--产生行同步脉冲和行de
hcount: BLOCK 
SIGNAL hz : std_logic;
BEGIN
PROCESS (clk,hz)
BEGIN
IF (hz = '1') THEN
hcountreg <= (OTHERS =>'0');
ELSIF clk'event AND clk = '1' THEN
hcountreg <= hcountreg +1;
END IF;
END PROCESS;
hb <= '1' when hcountreg >=HBP+HSY AND hcountreg <HBP+HSY+HAC 
ELSE '0';