image.tan.rpt

可以受上位机控制的通过fpga的视频信号发生器程序

; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C20F324C6       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                  ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------+----------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                 ; To                               ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------+----------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 86.36 MHz ( period = 11.579 ns )                    ; pos[3]                                               ; shinningblock:U2|color           ; clk        ; clk      ; None                        ; None                      ; 11.377 ns               ;
; N/A                                     ; 87.22 MHz ( period = 11.465 ns )                    ; pos[1]                                               ; shinningblock:U2|color           ; clk        ; clk      ; None                        ; None                      ; 11.263 ns               ;
; N/A                                     ; 88.61 MHz ( period = 11.286 ns )                    ; pos[2]                                               ; shinningblock:U2|color           ; clk        ; clk      ; None                        ; None                      ; 11.084 ns               ;
; N/A                                     ; 88.82 MHz ( period = 11.259 ns )                    ; pos[0]                                               ; shinningblock:U2|color           ; clk        ; clk      ; None                        ; None                      ; 11.057 ns               ;
; N/A                                     ; 90.52 MHz ( period = 11.047 ns )                    ; time2[3]                                             ; moving_object:U1|nn[30]          ; clk        ; clk      ; None                        ; None                      ; 10.768 ns               ;
; N/A                                     ; 90.52 MHz ( period = 11.047 ns )                    ; time2[3]                                             ; moving_object:U1|nn[31]          ; clk        ; clk      ; None                        ; None                      ; 10.768 ns               ;
; N/A                                     ; 90.69 MHz ( period = 11.027 ns )                    ; time2[2]                                             ; moving_object:U1|nn[30]          ; clk        ; clk      ; None                        ; None                      ; 10.748 ns               ;
; N/A                                     ; 90.69 MHz ( period = 11.027 ns )                    ; time2[2]                                             ; moving_object:U1|nn[31]          ; clk        ; clk      ; None                        ; None                      ; 10.748 ns               ;
; N/A                                     ; 91.02 MHz ( period = 10.987 ns )                    ; time2[3]                                             ; moving_object:U1|nn[29]          ; clk        ; clk      ; None                        ; None                      ; 10.708 ns               ;
; N/A                                     ; 91.02 MHz ( period = 10.987 ns )                    ; time2[3]                                             ; moving_object:U1|nn[28]          ; clk        ; clk      ; None                        ; None                      ; 10.708 ns               ;
; N/A                                     ; 91.02 MHz ( period = 10.987 ns )                    ; time2[3]                                             ; moving_object:U1|nn[27]          ; clk        ; clk      ; None                        ; None                      ; 10.708 ns               ;
; N/A                                     ; 91.02 MHz ( period = 10.987 ns )                    ; time2[3]                                             ; moving_object:U1|nn[26]          ; clk        ; clk      ; None                        ; None                      ; 10.708 ns               ;
; N/A                                     ; 91.02 MHz ( period = 10.987 ns )                    ; time2[3]                                             ; moving_object:U1|nn[25]          ; clk        ; clk      ; None                        ; None                      ; 10.708 ns               ;
; N/A                                     ; 91.09 MHz ( period = 10.978 ns )                    ; hcountreg[2]                                         ; moving_object:U1|ad1b[0]         ; clk        ; clk      ; None                        ; None                      ; 10.776 ns               ;
; N/A                                     ; 91.10 MHz ( period = 10.977 ns )                    ; hcountreg[2]                                         ; moving_object:U1|ad1b[5]         ; clk        ; clk      ; None                        ; None                      ; 10.775 ns               ;
; N/A                                     ; 91.10 MHz ( period = 10.977 ns )                    ; hcountreg[2]                                         ; moving_object:U1|ad1b[4]         ; clk        ; clk      ; None                        ; None                      ; 10.775 ns               ;
; N/A                                     ; 91.11 MHz ( period = 10.976 ns )                    ; hcountreg[2]                                         ; moving_object:U1|ad1b[1]         ; clk        ; clk      ; None                        ; None                      ; 10.774 ns               ;
; N/A                                     ; 91.18 MHz ( period = 10.967 ns )                    ; time2[2]                                             ; moving_object:U1|nn[29]          ; clk        ; clk      ; None                        ; None                      ; 10.688 ns               ;
; N/A                                     ; 91.18 MHz ( period = 10.967 ns )                    ; time2[2]                                             ; moving_object:U1|nn[28]          ; clk        ; clk      ; None                        ; None                      ; 10.688 ns               ;
; N/A                                     ; 91.18 MHz ( period = 10.967 ns )                    ; time2[2]                                             ; moving_object:U1|nn[27]          ; clk        ; clk      ; None                        ; None                      ; 10.688 ns               ;
; N/A                                     ; 91.18 MHz ( period = 10.967 ns )                    ; time2[2]                                             ; moving_object:U1|nn[26]          ; clk        ; clk      ; None                        ; None                      ; 10.688 ns               ;