op3.vhd

可以受上位机控制的通过fpga的视频信号发生器程序

LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY op3 IS PORT
( clk    : IN std_logic;
  vcount : IN std_logic_vector(11 DOWNTO 0);
  hcount : IN std_logic_vector(10 DOWNTO 0);
  clken_fcount: IN std_logic;
  pattern: IN std_logic_vector(3  DOWNTO 0);
  distance:IN std_logic_vector(3  DOWNTO 0);
  wren    : IN std_logic;
  mode    : IN std_logic;
  sel       : IN  std_logic_vector(7 DOWNTO 0);
  address   : IN  std_logic_vector(7 DOWNTO 0);
  date      : IN  std_logic_vector(7 DOWNTO 0);
  out_r_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_g_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_b_e   : OUT std_logic_vector(7 DOWNTO 0);
  out_r_o   : OUT std_logic_vector(7 DOWNTO 0);
  out_g_o   : OUT std_logic_vector(7 DOWNTO 0);
  out_b_o   : OUT std_logic_vector(7 DOWNTO 0)
);
CONSTANT HAC:integer:=640;   -- horizontal active pixels 1448*1151
CONSTANT HSY:integer:=20;     -- horizontal sync width (negative polarity)
CONSTANT HBP:integer:=20;     -- horizontal back porch
CONSTANT VAC:integer:=1024;    -- vertical active pixels
CONSTANT VSY:integer:=25;      -- vertical sync width (negative polarity)
CONSTANT VBP:integer:=25;     -- vertical back porch

END op3;
ARCHITECTURE rtl OF op3 IS
	SIGNAL nn,speed,dist: integer;
	SIGNAL color : std_logic_vector(1 DOWNTO 0);
	SIGNAL address_a: STD_LOGIC_VECTOR(10 DOWNTO 0);
	SIGNAL address_b: STD_LOGIC_VECTOR(10 DOWNTO 0);
	signal ada:STD_LOGIC_VECTOR(7 DOWNTO 0);
	signal adb:STD_LOGIC_VECTOR(7 DOWNTO 0);
	SIGNAL q_a:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL q_b:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL front:STD_LOGIC_VECTOR(7 DOWNTO 0);
    SIGNAL back:STD_LOGIC_VECTOR(7 DOWNTO 0);
COMPONENT ram2 IS
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wraddress		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rdaddress_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rdaddress_b		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wren		: IN STD_LOGIC  := '1';
		clock		: IN STD_LOGIC ;
		qa		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		qb		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END COMPONENT;

BEGIN
u1: ram2
port map
(  
data=>date,
wraddress=>address,
rdaddress_a=>ada,
rdaddress_b=>adb,
wren=>wren,
clock=>clk,
qa=>q_a,
qb=>q_b
);

PROCESS(distance)
BEGIN
CASE distance IS
	WHEN  "0000"=>dist<=25;
	WHEN  "0001"=>dist<=50;
	WHEN  "0010"=>dist<=75;
    WHEN  "0011"=>dist<=100;
    WHEN  "0100"=>dist<=125;
    WHEN  "0101"=>dist<=150;
    WHEN  "0110"=>dist<=175;
    WHEN  "0111"=>dist<=200;
    WHEN  "1000"=>dist<=225;
    WHEN  "1001"=>dist<=250;
    When others =>dist<=0;
END CASE;
END PROCESS;

PROCESS(sel)
BEGIN
CASE sel IS
    WHEN  "00000000"=>back<="00000000";
                  front<="00110010";
	WHEN  "00000001"=>back<="00000000";
	              front<="01001110";
	WHEN  "00000010"=>back<="00000000";
	              front<="01101111";
    WHEN  "00000011"=>back<="00000000";
                  front<="10010110";
    WHEN  "00000100"=>back<="00000000";
                  front<="11000100";
    WHEN  "00000101"=>back<="00000000";
                  front<="11111111";
    
    WHEN  "00000110"=>back<="00110010";
                  front<="01001110";
    WHEN  "00000111"=>back<="00110010";
                  front<="01101111";
    WHEN  "00001000"=>back<="00110010";
                  front<="10010110";
    WHEN  "00001001"=>back<="00110010";
                  front<="11000100";
    WHEN  "00001010"=>back<="00110010";
                  front<="11111111";

    WHEN  "00001011"=>back<="01001110";
                  front<="01101111";
    WHEN  "00001100"=>back<="01001110";
                  front<="10010110"; 
    WHEN  "00001101"=>back<="01001110";
                  front<="11000100";
    WHEN  "00001110"=>back<="01001110";
                  front<="11111111";
     
WHEN  "00001111"=>back<="01101111";
                  front<="10010110";
 WHEN  "00010000"=>back<="01101111";
                  front<="11000100";
 WHEN  "00010001"=>back<="01101111";
                  front<="11111111";

 WHEN  "00010010"=>back<="10010110";
                  front<="11000100";
 WHEN  "00010011"=>back<="10010110";
                  front<="11111111";

WHEN  "00010100"=>back<="11000100";
                  front<="11111111";


    When others=>back<="00000000";
                 front<="00000000";
END CASE;
END PROCESS;

process(clk)
BEGIN
IF clk'event AND clk='1' THEN
if hcount>=170+HBP+HSY and hcount<270+HBP+HSY 
then
address_a<=hcount+hcount-HBP-HSY-HBP-HSY-340;
address_b<=hcount+hcount-HBP-HSY-HBP-HSY-339;
elsif hcount>=270+HBP+HSY and hcount<370+HBP+HSY
then
address_a<=hcount+hcount-HBP-HSY-HBP-HSY-540;
address_b<=hcount+hcount-HBP-HSY-HBP-HSY-539; 
elsif hcount>=370+HBP+HSY and hcount<470+HBP+HSY
then
address_a<=hcount+hcount-HBP-HSY-HBP-HSY-740;
address_b<=hcount+hcount-HBP-HSY-HBP-HSY-739; 
else 
address_a<="00000000000";
address_b<="00000000000";
end if;
end if;
end process;
ada<=address_a(7 downto 0);
adb<=address_b(7 downto 0);
speed<=conv_integer(pattern);

PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
IF vcount>=412+VBP+VSY-25 AND vcount<512+VBP+VSY-25 
then 
if mode='1'
then
if (hcount>=220+HBP+HSY and hcount<270+HBP+HSY)
or (hcount>=320+HBP+HSY and hcount<370+HBP+HSY)
or (hcount>=420+HBP+HSY and hcount<470+HBP+HSY) 
then
color<="01";
else color<="00";
end if;
elsif
   (hcount>=170+HBP+HSY and hcount<220+HBP+HSY)
or (hcount>=270+HBP+HSY and hcount<320+HBP+HSY)
or (hcount>=370+HBP+HSY and hcount<420+HBP+HSY) 
then
color<="01";
else color<="00";
end if;

elsif vcount>=512+VBP+VSY+25 AND vcount<612+VBP+VSY+25 
then if hcount>=245-dist+HBP+HSY AND hcount<(nn+HBP+HSY) 
THEN color<="10";
ELSif hcount>=nn+HBP+HSY AND hcount<(395+dist+HBP+HSY)  
then
color<="11";
else color<="00";
end if;
else color<="00";
END IF;
END IF;
END PROCESS;

PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
IF clken_fcount='1' THEN
IF nn>=395+dist THEN 
nn<=245-dist;
ELSE
nn<=(nn+speed);
END IF;
END IF;
END IF;
END PROCESS;

PROCESS(clk)
BEGIN
IF clk'event AND clk='1' THEN
if mode='1' then
IF color="01" THEN
out_r_e<=q_a;
out_g_e<=q_a;
out_b_e<=q_a;
out_r_o<=q_b;
out_g_o<=q_b;
out_b_o<=q_b;
ELSIF color="10" THEN
out_r_e<=front;
out_g_e<=front;
out_b_e<=front;
out_r_o<=front;
out_g_o<=front;
out_b_o<=front;
ELSE
out_r_e<=back;
out_g_e<=back;
out_b_e<=back;
out_r_o<=back;
out_g_o<=back;
out_b_o<=back;
END IF;
elsIF color="01" THEN
out_r_e<=q_a;
out_g_e<=q_a;
out_b_e<=q_a;
out_r_o<=q_b;
out_g_o<=q_b;
out_b_o<=q_b;
ELSIF color="10" THEN
out_r_e<=back;
out_g_e<=back;
out_b_e<=back;
out_r_o<=back;
out_g_o<=back;
out_b_o<=back;
ELSif color="11"
then
out_r_e<=front;
out_g_e<=front;
out_b_e<=front;
out_r_o<=front;
out_g_o<=front;
out_b_o<=front;
else
out_r_e<=back;
out_g_e<=back;
out_b_e<=back;
out_r_o<=back;
out_g_o<=back;
out_b_o<=back;
end if;
end if;
END PROCESS;


END rtl;