add_function.vhd

此为FPGA上的一个串口通信程序

--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use WORK.UART_PACKAGE.all;

entity add_function is
generic(DATA_BIT:integer:=8);
port(recv_over:in std_logic;
	 clk:in std_logic;
	 reset_n: in std_logic;
	 sending:in std_logic;
	 send:out std_logic;
	 recv_buf:in std_logic_vector(DATA_BIT-1 downto 0);
	 send_buf:out std_logic_vector(DATA_BIT-1 downto 0));
end add_function;

architecture add_function of add_function is 
signal count:integer:=1;
signal lab:std_logic;
begin
	main: process(clk,reset_n)
		begin
			if reset_n='1' then 
				send_buf<="00000000";
				send<='0';
				lab<='0';
				count<=1;
			elsif rising_edge(clk) and recv_over='1' then
				if recv_buf(7 downto 0)="00000000" then
					send_buf<="01010101";
					send <='1';
				else 
					send_buf<="10101010";
					send<='1';
				end if;
			elsif rising_edge(clk) and sending='0' and lab='0' then
				if count=1 then 	
					send_buf<="10011001";
					send <='1';
					lab<='1';
					count<=count+1;
				elsif count =2 then
					send_buf<="10011000";
					send<='1';
					lab<='1';
					count<=count+1;
				elsif count=3 then 
					send_buf<="10010111";
					send<='1';
					lab<='1';
					count<=count+1;
				elsif count=4 then
					send_buf<="10010110";
					send<='1';
					lab<='1';
					count<=count+1;
				elsif count=5 then 
					send_buf<="10010101";
					send<='1';
					lab<='1';
					count<=count+1;
				--elsif count=6 then
					--send_buf<="11111111";
					--send<='1';
					--lab<='1';
					--count<=7;
				--elsif count=7 then 
					--send_buf<="00000000";
					--send<='1';
					--lab<='1';
					--count<=6;
				end if;
			elsif rising_edge(clk) and sending='1' then 
				send <='0';
				lab<='0';
			
			end if;
	end process;
end add_function;