counter.vhd

来自「此为FPGA上的一个串口通信程序」· VHDL 代码 · 共 35 行

--
library IEEE;
use IEEE.STD_LOGIC_1164.all;

--
entity counter is
	generic(MAX_COUNT:integer:=8);
	
	port(clk:in std_logic;
		 reset_n:in std_logic;
		 ce:in std_logic;
		 overflow:out std_logic);
end counter;

architecture counter of counter is 
signal count:integer;
begin 
	main:process(clk,reset_n)
	begin
		if reset_n='0' then 
			count<=0;
			overflow<='0';
		elsif rising_edge(clk) and ce='1' then 
			if count=MAX_COUNT-1 then 
				count<=0;
				overflow<='1';
			elsif count=0 then 
				count<=count+1;
				overflow<='0';
			else 
				count<=count+1;
			end if;
		end if;
	end process;
end counter;