baudrate_generator.vhd

此为FPGA上的一个串口通信程序

--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use WORK.UART_PACKAGE.ALL;

--
entity baudrate_generator is
	--
	generic(
	FULL_PULSE_COUNT:BD_COUNT:=BD9600_FPC;
	RISE_PULSE_COUNT:BD_COUNT:=BD9600_HPC);
	--
	port(clk:in std_logic;
		 reset_n:in std_logic;
		 ce:in std_logic;
		 bg_out:out std_logic;
		 indicator:out std_logic);
end baudrate_generator;

--
architecture baudrate_generator of baudrate_generator is
begin
	main:process(clk,reset_n)
	variable clk_count:BD_COUNT;
	begin
		--
		if reset_n='0' then 
			bg_out<='0';
			indicator<='0';
			clk_count:=0;
		--
		elsif rising_edge(clk) then 
			--
			if ce='1' then 
				--
				if clk_count=RISE_PULSE_COUNT-1 then 
					bg_out<='1';
					clk_count:=clk_count+1;
				--
				elsif clk_count=FULL_PULSE_COUNT-1 then 
					indicator<='1';
					bg_out<='0';
					clk_count:=0;
				--
				elsif clk_count=0 then 
					indicator<='0';
					clk_count:=clk_count+1;
				else 
					clk_count:=clk_count+1;
				end if;
			end if;
		end if;
	end process;
end baudrate_generator;