parity_verifier.vhd

来自「此为FPGA上的一个串口通信程序」· VHDL 代码 · 共 21 行

--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use WORK.UART_PACKAGE.ALL;

--
entity parity_verifier is 
	generic(DATA_LENGTH:integer:=8;
			PARITY_RULE:PARITY:=NONE);
			
	port(source:in std_logic_vector(DATA_LENGTH-1 downto 0);
		 parity:out std_logic);
end parity_verifier;

architecture parity_verifier of parity_verifier is
begin
	with PARITY_RULE select
	parity<= MultiXOR(source) when ODD,
				(not MultiXOR(source)) when EVEN,
				'1' when others;
end parity_verifier;