qiangdaqi.sim.rpt

实现抢答器功能

; |qiangdaqi|clkin                  ; |qiangdaqi|clkin~corein           ; data_out0        ;
; |qiangdaqi|sh[0]                  ; |qiangdaqi|sh[0]                  ; padio            ;
; |qiangdaqi|sh[1]                  ; |qiangdaqi|sh[1]                  ; padio            ;
; |qiangdaqi|sl[0]                  ; |qiangdaqi|sl[0]                  ; padio            ;
; |qiangdaqi|sl[1]                  ; |qiangdaqi|sl[1]                  ; padio            ;
; |qiangdaqi|sl[2]                  ; |qiangdaqi|sl[2]                  ; padio            ;
; |qiangdaqi|sl[3]                  ; |qiangdaqi|sl[3]                  ; padio            ;
+-----------------------------------+-----------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                       ;
+--------------------------------------+--------------------------------------+------------------+
; Node Name                            ; Output Port Name                     ; Output Port Type ;
+--------------------------------------+--------------------------------------+------------------+
; |qiangdaqi|qiangda:u1|data[0]        ; |qiangdaqi|qiangda:u1|data[0]        ; data_out0        ;
; |qiangdaqi|qiangda:u1|data[1]        ; |qiangdaqi|qiangda:u1|data[1]        ; data_out0        ;
; |qiangdaqi|qiangda:u1|data[2]        ; |qiangdaqi|qiangda:u1|data[2]        ; data_out0        ;
; |qiangdaqi|daoji3:u3|CQI[3]          ; |qiangdaqi|daoji3:u3|CQI[3]          ; data_out0        ;
; |qiangdaqi|qiangda:u1|Mux2~272       ; |qiangdaqi|qiangda:u1|Mux2~272       ; data_out0        ;
; |qiangdaqi|qiangda:u1|flag           ; |qiangdaqi|qiangda:u1|flag           ; data_out0        ;
; |qiangdaqi|qiangda:u1|flag~260       ; |qiangdaqi|qiangda:u1|flag~260       ; data_out0        ;
; |qiangdaqi|qiangda:u1|Mux1~272       ; |qiangdaqi|qiangda:u1|Mux1~272       ; data_out0        ;
; |qiangdaqi|qiangda:u1|data[2]~100    ; |qiangdaqi|qiangda:u1|data[2]~100    ; data_out0        ;
; |qiangdaqi|qiangda:u1|Mux0~272       ; |qiangdaqi|qiangda:u1|Mux0~272       ; data_out0        ;
; |qiangdaqi|qiangda:u1|Mux3~446       ; |qiangdaqi|qiangda:u1|Mux3~446       ; data_out0        ;
; |qiangdaqi|qiangda:u1|Mux3~447       ; |qiangdaqi|qiangda:u1|Mux3~447       ; data_out0        ;
; |qiangdaqi|qiangda:u1|Mux3~448       ; |qiangdaqi|qiangda:u1|Mux3~448       ; data_out0        ;
; |qiangdaqi|qiangda:u1|Mux3~449       ; |qiangdaqi|qiangda:u1|Mux3~449       ; data_out0        ;
; |qiangdaqi|qiangda:u1|successful~164 ; |qiangdaqi|qiangda:u1|successful~169 ; cascout          ;
; |qiangdaqi|qiangda:u1|successful~167 ; |qiangdaqi|qiangda:u1|successful~167 ; data_out0        ;
; |qiangdaqi|sin[3]                    ; |qiangdaqi|sin[3]~corein             ; data_out0        ;
; |qiangdaqi|sin[0]                    ; |qiangdaqi|sin[0]~corein             ; data_out0        ;
; |qiangdaqi|sin[4]                    ; |qiangdaqi|sin[4]~corein             ; data_out0        ;
; |qiangdaqi|sin[2]                    ; |qiangdaqi|sin[2]~corein             ; data_out0        ;
; |qiangdaqi|sin[6]                    ; |qiangdaqi|sin[6]~corein             ; data_out0        ;
; |qiangdaqi|sin[1]                    ; |qiangdaqi|sin[1]~corein             ; data_out0        ;
; |qiangdaqi|sin[5]                    ; |qiangdaqi|sin[5]~corein             ; data_out0        ;
; |qiangdaqi|dt[0]                     ; |qiangdaqi|dt[0]                     ; padio            ;
; |qiangdaqi|dt[1]                     ; |qiangdaqi|dt[1]                     ; padio            ;
; |qiangdaqi|dt[2]                     ; |qiangdaqi|dt[2]                     ; padio            ;
; |qiangdaqi|dt[3]                     ; |qiangdaqi|dt[3]                     ; padio            ;
; |qiangdaqi|sh[2]                     ; |qiangdaqi|sh[2]                     ; padio            ;
; |qiangdaqi|sh[3]                     ; |qiangdaqi|sh[3]                     ; padio            ;
+--------------------------------------+--------------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                 ;
+-----------------------------------+-----------------------------------+------------------+
; Node Name                         ; Output Port Name                  ; Output Port Type ;
+-----------------------------------+-----------------------------------+------------------+
; |qiangdaqi|qiangda:u1|data[0]     ; |qiangdaqi|qiangda:u1|data[0]     ; data_out0        ;
; |qiangdaqi|qiangda:u1|data[1]     ; |qiangdaqi|qiangda:u1|data[1]     ; data_out0        ;
; |qiangdaqi|qiangda:u1|data[2]     ; |qiangdaqi|qiangda:u1|data[2]     ; data_out0        ;
; |qiangdaqi|daoji3:u3|CQI[3]       ; |qiangdaqi|daoji3:u3|CQI[3]       ; data_out0        ;
; |qiangdaqi|qiangda:u1|data[1]~97  ; |qiangdaqi|qiangda:u1|data[1]~97  ; data_out0        ;
; |qiangdaqi|qiangda:u1|Mux2~272    ; |qiangdaqi|qiangda:u1|Mux2~272    ; data_out0        ;
; |qiangdaqi|qiangda:u1|flag        ; |qiangdaqi|qiangda:u1|flag        ; data_out0        ;
; |qiangdaqi|qiangda:u1|Mux1~272    ; |qiangdaqi|qiangda:u1|Mux1~272    ; data_out0        ;
; |qiangdaqi|qiangda:u1|data[2]~100 ; |qiangdaqi|qiangda:u1|data[2]~100 ; data_out0        ;
; |qiangdaqi|qiangda:u1|Mux0~272    ; |qiangdaqi|qiangda:u1|Mux0~272    ; data_out0        ;
; |qiangdaqi|qiangda:u1|successful  ; |qiangdaqi|qiangda:u1|successful  ; data_out0        ;
; |qiangdaqi|qiangda:u1|Mux3~446    ; |qiangdaqi|qiangda:u1|Mux3~446    ; data_out0        ;
; |qiangdaqi|qiangda:u1|Mux3~447    ; |qiangdaqi|qiangda:u1|Mux3~447    ; data_out0        ;
; |qiangdaqi|qiangda:u1|Mux3~448    ; |qiangdaqi|qiangda:u1|Mux3~448    ; data_out0        ;
; |qiangdaqi|qiangda:u1|Mux3~449    ; |qiangdaqi|qiangda:u1|Mux3~449    ; data_out0        ;
; |qiangdaqi|startin                ; |qiangdaqi|startin~corein         ; data_out0        ;
; |qiangdaqi|sin[3]                 ; |qiangdaqi|sin[3]~corein          ; data_out0        ;
; |qiangdaqi|sin[0]                 ; |qiangdaqi|sin[0]~corein          ; data_out0        ;
; |qiangdaqi|sin[4]                 ; |qiangdaqi|sin[4]~corein          ; data_out0        ;
; |qiangdaqi|sin[2]                 ; |qiangdaqi|sin[2]~corein          ; data_out0        ;
; |qiangdaqi|sin[6]                 ; |qiangdaqi|sin[6]~corein          ; data_out0        ;
; |qiangdaqi|sin[1]                 ; |qiangdaqi|sin[1]~corein          ; data_out0        ;
; |qiangdaqi|sin[5]                 ; |qiangdaqi|sin[5]~corein          ; data_out0        ;
; |qiangdaqi|dt[0]                  ; |qiangdaqi|dt[0]                  ; padio            ;
; |qiangdaqi|dt[1]                  ; |qiangdaqi|dt[1]                  ; padio            ;
; |qiangdaqi|dt[2]                  ; |qiangdaqi|dt[2]                  ; padio            ;
; |qiangdaqi|dt[3]                  ; |qiangdaqi|dt[3]                  ; padio            ;
; |qiangdaqi|sh[2]                  ; |qiangdaqi|sh[2]                  ; padio            ;
; |qiangdaqi|sh[3]                  ; |qiangdaqi|sh[3]                  ; padio            ;
+-----------------------------------+-----------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Fri Apr 11 11:20:38 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off qiangdaqi -c qiangdaqi
Info: Using vector source file "E:/ѧϰ/EDA/qiangdaqi/qiangdaqi.vwf"
Info: Inverted registers were found during simulation
    Info: Register: |qiangdaqi|daoji3:u3|CQI[0]
    Info: Register: |qiangdaqi|daoji3:u3|CQI[1]
    Info: Register: |qiangdaqi|daoji10:u2|CQI[0]
    Info: Register: |qiangdaqi|daoji10:u2|CQI[3]
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      30.43 %
Info: Number of transitions in simulation is 345
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 98 megabytes of memory during processing
    Info: Processing ended: Fri Apr 11 11:20:43 2008
    Info: Elapsed time: 00:00:05