qiangdaqi.tan.qmsg

实现抢答器功能

{ "Info" "ITDB_TSU_RESULT" "qiangda:u1\|successful sin\[4\] clkin 6.528 ns register " "Info: tsu for register \"qiangda:u1\|successful\" (data pin = \"sin\[4\]\", clock pin = \"clkin\") is 6.528 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "17.348 ns + Longest pin register " "Info: + Longest pin to register delay is 17.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.070 ns) 2.070 ns sin\[4\] 1 PIN PIN_20 5 " "Info: 1: + IC(0.000 ns) + CELL(2.070 ns) = 2.070 ns; Loc. = PIN_20; Fanout = 5; PIN Node = 'sin\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sin[4] } "NODE_NAME" } } { "qiangdaqi.vhd" "" { Text "E:/ѧϰ/EDA/qiangdaqi/qiangdaqi.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(9.173 ns) + CELL(1.278 ns) 12.521 ns qiangda:u1\|Mux3~448 2 COMB LC7_9_J2 1 " "Info: 2: + IC(9.173 ns) + CELL(1.278 ns) = 12.521 ns; Loc. = LC7_9_J2; Fanout = 1; COMB Node = 'qiangda:u1\|Mux3~448'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.451 ns" { sin[4] qiangda:u1|Mux3~448 } "NODE_NAME" } } { "qiangda.vhd" "" { Text "E:/ѧϰ/EDA/qiangdaqi/qiangda.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.112 ns) + CELL(1.428 ns) 15.061 ns qiangda:u1\|Mux3~449 3 COMB LC9_9_J2 2 " "Info: 3: + IC(1.112 ns) + CELL(1.428 ns) = 15.061 ns; Loc. = LC9_9_J2; Fanout = 2; COMB Node = 'qiangda:u1\|Mux3~449'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.540 ns" { qiangda:u1|Mux3~448 qiangda:u1|Mux3~449 } "NODE_NAME" } } { "qiangda.vhd" "" { Text "E:/ѧϰ/EDA/qiangdaqi/qiangda.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.304 ns) + CELL(1.428 ns) 16.793 ns qiangda:u1\|successful~167 4 COMB LC9_10_J2 1 " "Info: 4: + IC(0.304 ns) + CELL(1.428 ns) = 16.793 ns; Loc. = LC9_10_J2; Fanout = 1; COMB Node = 'qiangda:u1\|successful~167'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.732 ns" { qiangda:u1|Mux3~449 qiangda:u1|successful~167 } "NODE_NAME" } } { "qiangda.vhd" "" { Text "E:/ѧϰ/EDA/qiangdaqi/qiangda.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.287 ns) + CELL(0.268 ns) 17.348 ns qiangda:u1\|successful 5 REG LC10_10_J2 12 " "Info: 5: + IC(0.287 ns) + CELL(0.268 ns) = 17.348 ns; Loc. = LC10_10_J2; Fanout = 12; REG Node = 'qiangda:u1\|successful'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.555 ns" { qiangda:u1|successful~167 qiangda:u1|successful } "NODE_NAME" } } { "qiangda.vhd" "" { Text "E:/ѧϰ/EDA/qiangdaqi/qiangda.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.472 ns ( 37.31 % ) " "Info: Total cell delay = 6.472 ns ( 37.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.876 ns ( 62.69 % ) " "Info: Total interconnect delay = 10.876 ns ( 62.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "17.348 ns" { sin[4] qiangda:u1|Mux3~448 qiangda:u1|Mux3~449 qiangda:u1|successful~167 qiangda:u1|successful } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "17.348 ns" { sin[4] {} sin[4]~out0 {} qiangda:u1|Mux3~448 {} qiangda:u1|Mux3~449 {} qiangda:u1|successful~167 {} qiangda:u1|successful {} } { 0.000ns 0.000ns 9.173ns 1.112ns 0.304ns 0.287ns } { 0.000ns 2.070ns 1.278ns 1.428ns 1.428ns 0.268ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.167 ns + " "Info: + Micro setup delay of destination is 0.167 ns" {  } { { "qiangda.vhd" "" { Text "E:/ѧϰ/EDA/qiangdaqi/qiangda.vhd" 10 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 10.987 ns - Shortest register " "Info: - Shortest clock path from clock \"clkin\" to destination register is 10.987 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.070 ns) 2.070 ns clkin 1 CLK PIN_180 10 " "Info: 1: + IC(0.000 ns) + CELL(2.070 ns) = 2.070 ns; Loc. = PIN_180; Fanout = 10; CLK Node = 'clkin'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "qiangdaqi.vhd" "" { Text "E:/ѧϰ/EDA/qiangdaqi/qiangdaqi.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(8.917 ns) + CELL(0.000 ns) 10.987 ns qiangda:u1\|successful 2 REG LC10_10_J2 12 " "Info: 2: + IC(8.917 ns) + CELL(0.000 ns) = 10.987 ns; Loc. = LC10_10_J2; Fanout = 12; REG Node = 'qiangda:u1\|successful'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.917 ns" { clkin qiangda:u1|successful } "NODE_NAME" } } { "qiangda.vhd" "" { Text "E:/ѧϰ/EDA/qiangdaqi/qiangda.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.070 ns ( 18.84 % ) " "Info: Total cell delay = 2.070 ns ( 18.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.917 ns ( 81.16 % ) " "Info: Total interconnect delay = 8.917 ns ( 81.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.987 ns" { clkin qiangda:u1|successful } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.987 ns" { clkin {} clkin~out0 {} qiangda:u1|successful {} } { 0.000ns 0.000ns 8.917ns } { 0.000ns 2.070ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "17.348 ns" { sin[4] qiangda:u1|Mux3~448 qiangda:u1|Mux3~449 qiangda:u1|successful~167 qiangda:u1|successful } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "17.348 ns" { sin[4] {} sin[4]~out0 {} qiangda:u1|Mux3~448 {} qiangda:u1|Mux3~449 {} qiangda:u1|successful~167 {} qiangda:u1|successful {} } { 0.000ns 0.000ns 9.173ns 1.112ns 0.304ns 0.287ns } { 0.000ns 2.070ns 1.278ns 1.428ns 1.428ns 0.268ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.987 ns" { clkin qiangda:u1|successful } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.987 ns" { clkin {} clkin~out0 {} qiangda:u1|successful {} } { 0.000ns 0.000ns 8.917ns } { 0.000ns 2.070ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clkin sh\[3\] daoji3:u3\|CQI\[3\] 24.096 ns register " "Info: tco from clock \"clkin\" to destination pin \"sh\[3\]\" through register \"daoji3:u3\|CQI\[3\]\" is 24.096 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 14.925 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to source register is 14.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.070 ns) 2.070 ns clkin 1 CLK PIN_180 10 " "Info: 1: + IC(0.000 ns) + CELL(2.070 ns) = 2.070 ns; Loc. = PIN_180; Fanout = 10; CLK Node = 'clkin'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "qiangdaqi.vhd" "" { Text "E:/ѧϰ/EDA/qiangdaqi/qiangdaqi.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(8.920 ns) + CELL(0.771 ns) 11.761 ns daoji10:u2\|CL 2 REG LC7_10_J2 6 " "Info: 2: + IC(8.920 ns) + CELL(0.771 ns) = 11.761 ns; Loc. = LC7_10_J2; Fanout = 6; REG Node = 'daoji10:u2\|CL'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.691 ns" { clkin daoji10:u2|CL } "NODE_NAME" } } { "daoji10.vhd" "" { Text "E:/ѧϰ/EDA/qiangdaqi/daoji10.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.164 ns) + CELL(0.000 ns) 14.925 ns daoji3:u3\|CQI\[3\] 3 REG LC3_11_J2 4 " "Info: 3: + IC(3.164 ns) + CELL(0.000 ns) = 14.925 ns; Loc. = LC3_11_J2; Fanout = 4; REG Node = 'daoji3:u3\|CQI\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.164 ns" { daoji10:u2|CL daoji3:u3|CQI[3] } "NODE_NAME" } } { "daoji3.vhd" "" { Text "E:/ѧϰ/EDA/qiangdaqi/daoji3.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.841 ns ( 19.04 % ) " "Info: Total cell delay = 2.841 ns ( 19.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.084 ns ( 80.96 % ) " "Info: Total interconnect delay = 12.084 ns ( 80.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.925 ns" { clkin daoji10:u2|CL daoji3:u3|CQI[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.925 ns" { clkin {} clkin~out0 {} daoji10:u2|CL {} daoji3:u3|CQI[3] {} } { 0.000ns 0.000ns 8.920ns 3.164ns } { 0.000ns 2.070ns 0.771ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.512 ns + " "Info: + Micro clock to output delay of source is 0.512 ns" {  } { { "daoji3.vhd" "" { Text "E:/ѧϰ/EDA/qiangdaqi/daoji3.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.659 ns + Longest register pin " "Info: + Longest register to pin delay is 8.659 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.259 ns) 0.259 ns daoji3:u3\|CQI\[3\] 1 REG LC3_11_J2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.259 ns) = 0.259 ns; Loc. = LC3_11_J2; Fanout = 4; REG Node = 'daoji3:u3\|CQI\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { daoji3:u3|CQI[3] } "NODE_NAME" } } { "daoji3.vhd" "" { Text "E:/ѧϰ/EDA/qiangdaqi/daoji3.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.689 ns) + CELL(2.711 ns) 8.659 ns sh\[3\] 2 PIN PIN_53 0 " "Info: 2: + IC(5.689 ns) + CELL(2.711 ns) = 8.659 ns; Loc. = PIN_53; Fanout = 0; PIN Node = 'sh\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.400 ns" { daoji3:u3|CQI[3] sh[3] } "NODE_NAME" } } { "qiangdaqi.vhd" "" { Text "E:/ѧϰ/EDA/qiangdaqi/qiangdaqi.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.970 ns ( 34.30 % ) " "Info: Total cell delay = 2.970 ns ( 34.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.689 ns ( 65.70 % ) " "Info: Total interconnect delay = 5.689 ns ( 65.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.659 ns" { daoji3:u3|CQI[3] sh[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.659 ns" { daoji3:u3|CQI[3] {} sh[3] {} } { 0.000ns 5.689ns } { 0.259ns 2.711ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.925 ns" { clkin daoji10:u2|CL daoji3:u3|CQI[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.925 ns" { clkin {} clkin~out0 {} daoji10:u2|CL {} daoji3:u3|CQI[3] {} } { 0.000ns 0.000ns 8.920ns 3.164ns } { 0.000ns 2.070ns 0.771ns 0.000ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.659 ns" { daoji3:u3|CQI[3] sh[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.659 ns" { daoji3:u3|CQI[3] {} sh[3] {} } { 0.000ns 5.689ns } { 0.259ns 2.711ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "daoji3:u3\|CL startin clkin 2.704 ns register " "Info: th for register \"daoji3:u3\|CL\" (data pin = \"startin\", clock pin = \"clkin\") is 2.704 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 14.931 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to destination register is 14.931 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.070 ns) 2.070 ns clkin 1 CLK PIN_180 10 " "Info: 1: + IC(0.000 ns) + CELL(2.070 ns) = 2.070 ns; Loc. = PIN_180; Fanout = 10; CLK Node = 'clkin'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "qiangdaqi.vhd" "" { Text "E:/ѧϰ/EDA/qiangdaqi/qiangdaqi.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(8.920 ns) + CELL(0.771 ns) 11.761 ns daoji10:u2\|CL 2 REG LC7_10_J2 6 " "Info: 2: + IC(8.920 ns) + CELL(0.771 ns) = 11.761 ns; Loc. = LC7_10_J2; Fanout = 6; REG Node = 'daoji10:u2\|CL'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.691 ns" { clkin daoji10:u2|CL } "NODE_NAME" } } { "daoji10.vhd" "" { Text "E:/ѧϰ/EDA/qiangdaqi/daoji10.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.170 ns) + CELL(0.000 ns) 14.931 ns daoji3:u3\|CL 3 REG LC3_10_J2 4 " "Info: 3: + IC(3.170 ns) + CELL(0.000 ns) = 14.931 ns; Loc. = LC3_10_J2; Fanout = 4; REG Node = 'daoji3:u3\|CL'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.170 ns" { daoji10:u2|CL daoji3:u3|CL } "NODE_NAME" } } { "daoji3.vhd" "" { Text "E:/ѧϰ/EDA/qiangdaqi/daoji3.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.841 ns ( 19.03 % ) " "Info: Total cell delay = 2.841 ns ( 19.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.090 ns ( 80.97 % ) " "Info: Total interconnect delay = 12.090 ns ( 80.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.931 ns" { clkin daoji10:u2|CL daoji3:u3|CL } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.931 ns" { clkin {} clkin~out0 {} daoji10:u2|CL {} daoji3:u3|CL {} } { 0.000ns 0.000ns 8.920ns 3.170ns } { 0.000ns 2.070ns 0.771ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.376 ns + " "Info: + Micro hold delay of destination is 0.376 ns" {  } { { "daoji3.vhd" "" { Text "E:/ѧϰ/EDA/qiangdaqi/daoji3.vhd" 10 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.603 ns - Shortest pin register " "Info: - Shortest pin to register delay is 12.603 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.070 ns) 2.070 ns startin 1 PIN PIN_11 17 " "Info: 1: + IC(0.000 ns) + CELL(2.070 ns) = 2.070 ns; Loc. = PIN_11; Fanout = 17; PIN Node = 'startin'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { startin } "NODE_NAME" } } { "qiangdaqi.vhd" "" { Text "E:/ѧϰ/EDA/qiangdaqi/qiangdaqi.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(9.393 ns) + CELL(1.140 ns) 12.603 ns daoji3:u3\|CL 2 REG LC3_10_J2 4 " "Info: 2: + IC(9.393 ns) + CELL(1.140 ns) = 12.603 ns; Loc. = LC3_10_J2; Fanout = 4; REG Node = 'daoji3:u3\|CL'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.533 ns" { startin daoji3:u3|CL } "NODE_NAME" } } { "daoji3.vhd" "" { Text "E:/ѧϰ/EDA/qiangdaqi/daoji3.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.210 ns ( 25.47 % ) " "Info: Total cell delay = 3.210 ns ( 25.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.393 ns ( 74.53 % ) " "Info: Total interconnect delay = 9.393 ns ( 74.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.603 ns" { startin daoji3:u3|CL } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "12.603 ns" { startin {} startin~out0 {} daoji3:u3|CL {} } { 0.000ns 0.000ns 9.393ns } { 0.000ns 2.070ns 1.140ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.931 ns" { clkin daoji10:u2|CL daoji3:u3|CL } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.931 ns" { clkin {} clkin~out0 {} daoji10:u2|CL {} daoji3:u3|CL {} } { 0.000ns 0.000ns 8.920ns 3.170ns } { 0.000ns 2.070ns 0.771ns 0.000ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.603 ns" { startin daoji3:u3|CL } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "12.603 ns" { startin {} startin~out0 {} daoji3:u3|CL {} } { 0.000ns 0.000ns 9.393ns } { 0.000ns 2.070ns 1.140ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "160 " "Info: Allocated 160 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 11 11:18:20 2008 " "Info: Processing ended: Fri Apr 11 11:18:20 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}