prev_cmp_qiangdaqi.qmsg

实现抢答器功能

{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "qiangda:u1\|data\[3\] data_in GND " "Warning (14130): Reduced register \"qiangda:u1\|data\[3\]\" with stuck data_in port to stuck value GND" {  } { { "qiangda.vhd" "" { Text "E:/学习/EDA/qiangdaqi/qiangda.vhd" 17 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "daoji3.vhd" "" { Text "E:/学习/EDA/qiangdaqi/daoji3.vhd" 20 -1 0 } } { "daoji3.vhd" "" { Text "E:/学习/EDA/qiangdaqi/daoji3.vhd" 20 -1 0 } } { "daoji10.vhd" "" { Text "E:/学习/EDA/qiangdaqi/daoji10.vhd" 20 -1 0 } } { "daoji10.vhd" "" { Text "E:/学习/EDA/qiangdaqi/daoji10.vhd" 20 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "dt\[3\] GND " "Warning (13410): Pin \"dt\[3\]\" stuck at GND" {  } { { "qiangdaqi.vhd" "" { Text "E:/学习/EDA/qiangdaqi/qiangdaqi.vhd" 9 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "52 " "Info: Implemented 52 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "9 " "Info: Implemented 9 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "31 " "Info: Implemented 31 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "159 " "Info: Allocated 159 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 11 11:16:25 2008 " "Info: Processing ended: Fri Apr 11 11:16:25 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 11 11:16:36 2008 " "Info: Processing started: Fri Apr 11 11:16:36 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off qiangdaqi -c qiangdaqi " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off qiangdaqi -c qiangdaqi" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "qiangdaqi EP20K300EQC240-3 " "Info: Selected device EP20K300EQC240-3 for design \"qiangdaqi\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "" 0}