qiangdaqi.map.qmsg

实现抢答器功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 11 11:16:13 2008 " "Info: Processing started: Fri Apr 11 11:16:13 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off qiangdaqi -c qiangdaqi " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off qiangdaqi -c qiangdaqi" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "daoji10.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file daoji10.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 daoji10-Behavioral " "Info: Found design unit 1: daoji10-Behavioral" {  } { { "daoji10.vhd" "" { Text "E:/学习/EDA/qiangdaqi/daoji10.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 daoji10 " "Info: Found entity 1: daoji10" {  } { { "daoji10.vhd" "" { Text "E:/学习/EDA/qiangdaqi/daoji10.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "daoji3.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file daoji3.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 daoji3-Behavioral " "Info: Found design unit 1: daoji3-Behavioral" {  } { { "daoji3.vhd" "" { Text "E:/学习/EDA/qiangdaqi/daoji3.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 daoji3 " "Info: Found entity 1: daoji3" {  } { { "daoji3.vhd" "" { Text "E:/学习/EDA/qiangdaqi/daoji3.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "qiangda.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file qiangda.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 qiangda-qia " "Info: Found design unit 1: qiangda-qia" {  } { { "qiangda.vhd" "" { Text "E:/学习/EDA/qiangdaqi/qiangda.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 qiangda " "Info: Found entity 1: qiangda" {  } { { "qiangda.vhd" "" { Text "E:/学习/EDA/qiangdaqi/qiangda.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "C:/Documents and Settings/Administrator/桌面/ttttt/qiangdaqi.vhd " "Warning: Can't analyze file -- file C:/Documents and Settings/Administrator/桌面/ttttt/qiangdaqi.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "qiangdaqi.vhd 2 1 " "Warning: Using design file qiangdaqi.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 qiangdaqi-Behavioral " "Info: Found design unit 1: qiangdaqi-Behavioral" {  } { { "qiangdaqi.vhd" "" { Text "E:/学习/EDA/qiangdaqi/qiangdaqi.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 qiangdaqi " "Info: Found entity 1: qiangdaqi" {  } { { "qiangdaqi.vhd" "" { Text "E:/学习/EDA/qiangdaqi/qiangdaqi.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "qiangdaqi " "Info: Elaborating entity \"qiangdaqi\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "qiangda qiangda:u1 " "Info: Elaborating entity \"qiangda\" for hierarchy \"qiangda:u1\"" {  } { { "qiangdaqi.vhd" "u1" { Text "E:/学习/EDA/qiangdaqi/qiangdaqi.vhd" 38 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "daoji10 daoji10:u2 " "Info: Elaborating entity \"daoji10\" for hierarchy \"daoji10:u2\"" {  } { { "qiangdaqi.vhd" "u2" { Text "E:/学习/EDA/qiangdaqi/qiangdaqi.vhd" 43 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "daoji3 daoji3:u3 " "Info: Elaborating entity \"daoji3\" for hierarchy \"daoji3:u3\"" {  } { { "qiangdaqi.vhd" "u3" { Text "E:/学习/EDA/qiangdaqi/qiangdaqi.vhd" 46 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "qiangda:u1\|data\[3\] data_in GND " "Warning (14130): Reduced register \"qiangda:u1\|data\[3\]\" with stuck data_in port to stuck value GND" {  } { { "qiangda.vhd" "" { Text "E:/学习/EDA/qiangdaqi/qiangda.vhd" 17 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "daoji3.vhd" "" { Text "E:/学习/EDA/qiangdaqi/daoji3.vhd" 20 -1 0 } } { "daoji3.vhd" "" { Text "E:/学习/EDA/qiangdaqi/daoji3.vhd" 20 -1 0 } } { "daoji10.vhd" "" { Text "E:/学习/EDA/qiangdaqi/daoji10.vhd" 20 -1 0 } } { "daoji10.vhd" "" { Text "E:/学习/EDA/qiangdaqi/daoji10.vhd" 20 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "dt\[3\] GND " "Warning (13410): Pin \"dt\[3\]\" stuck at GND" {  } { { "qiangdaqi.vhd" "" { Text "E:/学习/EDA/qiangdaqi/qiangdaqi.vhd" 9 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "52 " "Info: Implemented 52 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "9 " "Info: Implemented 9 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "31 " "Info: Implemented 31 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "159 " "Info: Allocated 159 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 11 11:16:25 2008 " "Info: Processing ended: Fri Apr 11 11:16:25 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}