qiangda.vhd

来自「实现抢答器功能」· VHDL 代码 · 共 47 行

library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity qiangda is 
port(      clk:in std_logic;
           suocuns:in std_logic;
           s:in std_logic_vector(6 downto 0);
           start:in std_logic;
           data: out std_logic_vector(3 downto 0);
           successful:out std_logic);
end qiangda;
architecture qia of qiangda is
signal flag: std_logic;
begin
  process(suocuns,start,s,flag,clk)
    begin
   if clk'event and clk='1' then
     if start='0' then data<="0000";successful<='0';flag<='0';
     elsif (start='1' and suocuns='0' and flag='0') then 
               case s is  
              when "0000001"=> data<="0001";successful<='1';flag<='1';
              when "0000010"=> data<="0010";
                                     successful<='1';flag<='1';
              when "0000100"=> data<="0011";
                                    successful<='1';flag<='1';
               when "0001000"=>data<="0100";
                                     successful<='1';flag<='1';
              when "0010000"=>data<="0101";
                                   successful<='1';flag<='1';
              when "0100000"=> data<="0110";
                                    successful<='1';flag<='1';
              when "1000000"=> data<="0111";
                                    successful<='1';flag<='1';
              when others=> data<="0000";successful<='0';flag<='0';
             end case;
     elsif suocuns='1' then successful<='1';
     end if;
end if;
  end process;
end;