qiangdaqi.map.rpt

实现抢答器功能

; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path        ;
+----------------------------------+-----------------+-----------------+-------------------------------------+
; daoji10.vhd                      ; yes             ; User VHDL File  ; E:/学习/EDA/qiangdaqi/daoji10.vhd   ;
; daoji3.vhd                       ; yes             ; User VHDL File  ; E:/学习/EDA/qiangdaqi/daoji3.vhd    ;
; qiangda.vhd                      ; yes             ; User VHDL File  ; E:/学习/EDA/qiangdaqi/qiangda.vhd   ;
; qiangdaqi.vhd                    ; yes             ; Other           ; E:/学习/EDA/qiangdaqi/qiangdaqi.vhd ;
+----------------------------------+-----------------+-----------------+-------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+--------------------------------+------------+
; Resource                       ; Usage      ;
+--------------------------------+------------+
; Total logic elements           ; 31         ;
; Total combinational functions  ; 31         ;
;     -- Total 4-input functions ; 19         ;
;     -- Total 3-input functions ; 5          ;
;     -- Total 2-input functions ; 3          ;
;     -- Total 1-input functions ; 4          ;
;     -- Total 0-input functions ; 0          ;
; Total registers                ; 15         ;
; I/O pins                       ; 21         ;
; Maximum fan-out node           ; startin    ;
; Maximum fan-out                ; 17         ;
; Total fan-out                  ; 149        ;
; Average fan-out                ; 2.87       ;
+--------------------------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                     ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name   ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------+--------------+
; |qiangdaqi                 ; 31 (0)      ; 15           ; 0           ; 21   ; 0            ; 16 (0)       ; 0 (0)             ; 15 (0)           ; 0 (0)           ; 0 (0)      ; |qiangdaqi            ; work         ;
;    |daoji10:u2|            ; 8 (8)       ; 5            ; 0           ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 5 (5)            ; 0 (0)           ; 0 (0)      ; |qiangdaqi|daoji10:u2 ; work         ;
;    |daoji3:u3|             ; 6 (6)       ; 5            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; 0 (0)           ; 0 (0)      ; |qiangdaqi|daoji3:u3  ; work         ;
;    |qiangda:u1|            ; 17 (17)     ; 5            ; 0           ; 0    ; 0            ; 12 (12)      ; 0 (0)             ; 5 (5)            ; 0 (0)           ; 0 (0)      ; |qiangdaqi|qiangda:u1 ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; qiangda:u1|data[3]                    ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 1 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 15    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 8     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 12    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; daoji3:u3|CQI[0]                       ; 6       ;
; daoji3:u3|CQI[1]                       ; 5       ;
; daoji10:u2|CQI[0]                      ; 6       ;
; daoji10:u2|CQI[3]                      ; 5       ;
; Total number of inverted registers = 4 ;         ;
+----------------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Fri Apr 11 11:16:13 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off qiangdaqi -c qiangdaqi
Info: Found 2 design units, including 1 entities, in source file daoji10.vhd
    Info: Found design unit 1: daoji10-Behavioral
    Info: Found entity 1: daoji10
Info: Found 2 design units, including 1 entities, in source file daoji3.vhd
    Info: Found design unit 1: daoji3-Behavioral
    Info: Found entity 1: daoji3
Info: Found 2 design units, including 1 entities, in source file qiangda.vhd
    Info: Found design unit 1: qiangda-qia
    Info: Found entity 1: qiangda
Warning: Can't analyze file -- file C:/Documents and Settings/Administrator/桌面/ttttt/qiangdaqi.vhd is missing
Warning: Using design file qiangdaqi.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: qiangdaqi-Behavioral
    Info: Found entity 1: qiangdaqi
Info: Elaborating entity "qiangdaqi" for the top level hierarchy
Info: Elaborating entity "qiangda" for hierarchy "qiangda:u1"
Info: Elaborating entity "daoji10" for hierarchy "daoji10:u2"
Info: Elaborating entity "daoji3" for hierarchy "daoji3:u3"
Warning (14130): Reduced register "qiangda:u1|data[3]" with stuck data_in port to stuck value GND
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "dt[3]" stuck at GND
Info: Implemented 52 device resources after synthesis - the final resource count might be different
    Info: Implemented 9 input pins
    Info: Implemented 12 output pins
    Info: Implemented 31 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
    Info: Allocated 159 megabytes of memory during processing
    Info: Processing ended: Fri Apr 11 11:16:25 2008
    Info: Elapsed time: 00:00:12