qiangdaqi.tan.rpt

实现抢答器功能

; N/A           ; None        ; -1.922 ns ; sin[3]  ; qiangda:u1|flag       ; clkin    ;
; N/A           ; None        ; -1.944 ns ; startin ; qiangda:u1|data[1]    ; clkin    ;
; N/A           ; None        ; -1.980 ns ; sin[0]  ; qiangda:u1|data[0]    ; clkin    ;
; N/A           ; None        ; -1.995 ns ; sin[3]  ; qiangda:u1|data[0]    ; clkin    ;
; N/A           ; None        ; -2.048 ns ; startin ; qiangda:u1|successful ; clkin    ;
; N/A           ; None        ; -2.098 ns ; startin ; daoji10:u2|CL         ; clkin    ;
; N/A           ; None        ; -2.533 ns ; sin[1]  ; qiangda:u1|data[1]    ; clkin    ;
; N/A           ; None        ; -2.535 ns ; sin[1]  ; qiangda:u1|data[2]    ; clkin    ;
; N/A           ; None        ; -2.539 ns ; startin ; qiangda:u1|data[0]    ; clkin    ;
; N/A           ; None        ; -2.562 ns ; sin[0]  ; qiangda:u1|data[2]    ; clkin    ;
; N/A           ; None        ; -2.676 ns ; sin[2]  ; qiangda:u1|flag       ; clkin    ;
; N/A           ; None        ; -2.684 ns ; sin[2]  ; qiangda:u1|data[0]    ; clkin    ;
; N/A           ; None        ; -2.734 ns ; sin[4]  ; qiangda:u1|data[0]    ; clkin    ;
; N/A           ; None        ; -3.401 ns ; sin[1]  ; qiangda:u1|flag       ; clkin    ;
; N/A           ; None        ; -3.428 ns ; sin[0]  ; qiangda:u1|flag       ; clkin    ;
; N/A           ; None        ; -3.601 ns ; sin[4]  ; qiangda:u1|successful ; clkin    ;
; N/A           ; None        ; -3.614 ns ; sin[3]  ; qiangda:u1|successful ; clkin    ;
; N/A           ; None        ; -4.368 ns ; sin[2]  ; qiangda:u1|successful ; clkin    ;
; N/A           ; None        ; -5.093 ns ; sin[1]  ; qiangda:u1|successful ; clkin    ;
; N/A           ; None        ; -5.120 ns ; sin[0]  ; qiangda:u1|successful ; clkin    ;
+---------------+-------------+-----------+---------+-----------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Fri Apr 11 11:18:17 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off qiangdaqi -c qiangdaqi
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clkin" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "daoji10:u2|CL" as buffer
Info: Clock "clkin" has Internal fmax of 144.32 MHz between source register "daoji3:u3|CL" and destination register "qiangda:u1|data[0]" (period= 6.929 ns)
    Info: + Longest register to register delay is 2.225 ns
        Info: 1: + IC(0.000 ns) + CELL(0.259 ns) = 0.259 ns; Loc. = LC3_10_J2; Fanout = 4; REG Node = 'daoji3:u3|CL'
        Info: 2: + IC(0.311 ns) + CELL(0.574 ns) = 1.144 ns; Loc. = LC10_9_J2; Fanout = 4; COMB Node = 'qiangda:u1|flag~260'
        Info: 3: + IC(0.266 ns) + CELL(0.815 ns) = 2.225 ns; Loc. = LC6_8_J2; Fanout = 1; REG Node = 'qiangda:u1|data[0]'
        Info: Total cell delay = 1.648 ns ( 74.07 % )
        Info: Total interconnect delay = 0.577 ns ( 25.93 % )
    Info: - Smallest clock skew is -4.025 ns
        Info: + Shortest clock path from clock "clkin" to destination register is 10.906 ns
            Info: 1: + IC(0.000 ns) + CELL(2.070 ns) = 2.070 ns; Loc. = PIN_180; Fanout = 10; CLK Node = 'clkin'
            Info: 2: + IC(8.836 ns) + CELL(0.000 ns) = 10.906 ns; Loc. = LC6_8_J2; Fanout = 1; REG Node = 'qiangda:u1|data[0]'
            Info: Total cell delay = 2.070 ns ( 18.98 % )
            Info: Total interconnect delay = 8.836 ns ( 81.02 % )
        Info: - Longest clock path from clock "clkin" to source register is 14.931 ns
            Info: 1: + IC(0.000 ns) + CELL(2.070 ns) = 2.070 ns; Loc. = PIN_180; Fanout = 10; CLK Node = 'clkin'
            Info: 2: + IC(8.920 ns) + CELL(0.771 ns) = 11.761 ns; Loc. = LC7_10_J2; Fanout = 6; REG Node = 'daoji10:u2|CL'
            Info: 3: + IC(3.170 ns) + CELL(0.000 ns) = 14.931 ns; Loc. = LC3_10_J2; Fanout = 4; REG Node = 'daoji3:u3|CL'
            Info: Total cell delay = 2.841 ns ( 19.03 % )
            Info: Total interconnect delay = 12.090 ns ( 80.97 % )
    Info: + Micro clock to output delay of source is 0.512 ns
    Info: + Micro setup delay of destination is 0.167 ns
Warning: Circuit may not operate. Detected 5 non-operational path(s) clocked by clock "clkin" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "qiangda:u1|successful" and destination pin or register "daoji3:u3|CL" for clock "clkin" (Hold time is 2.129 ns)
    Info: + Largest clock skew is 3.944 ns
        Info: + Longest clock path from clock "clkin" to destination register is 14.931 ns
            Info: 1: + IC(0.000 ns) + CELL(2.070 ns) = 2.070 ns; Loc. = PIN_180; Fanout = 10; CLK Node = 'clkin'
            Info: 2: + IC(8.920 ns) + CELL(0.771 ns) = 11.761 ns; Loc. = LC7_10_J2; Fanout = 6; REG Node = 'daoji10:u2|CL'
            Info: 3: + IC(3.170 ns) + CELL(0.000 ns) = 14.931 ns; Loc. = LC3_10_J2; Fanout = 4; REG Node = 'daoji3:u3|CL'
            Info: Total cell delay = 2.841 ns ( 19.03 % )
            Info: Total interconnect delay = 12.090 ns ( 80.97 % )
        Info: - Shortest clock path from clock "clkin" to source register is 10.987 ns
            Info: 1: + IC(0.000 ns) + CELL(2.070 ns) = 2.070 ns; Loc. = PIN_180; Fanout = 10; CLK Node = 'clkin'
            Info: 2: + IC(8.917 ns) + CELL(0.000 ns) = 10.987 ns; Loc. = LC10_10_J2; Fanout = 12; REG Node = 'qiangda:u1|successful'
            Info: Total cell delay = 2.070 ns ( 18.84 % )
            Info: Total interconnect delay = 8.917 ns ( 81.16 % )
    Info: - Micro clock to output delay of source is 0.512 ns
    Info: - Shortest register to register delay is 1.679 ns
        Info: 1: + IC(0.000 ns) + CELL(0.259 ns) = 0.259 ns; Loc. = LC10_10_J2; Fanout = 12; REG Node = 'qiangda:u1|successful'
        Info: 2: + IC(0.317 ns) + CELL(1.103 ns) = 1.679 ns; Loc. = LC3_10_J2; Fanout = 4; REG Node = 'daoji3:u3|CL'
        Info: Total cell delay = 1.362 ns ( 81.12 % )
        Info: Total interconnect delay = 0.317 ns ( 18.88 % )
    Info: + Micro hold delay of destination is 0.376 ns
Info: tsu for register "qiangda:u1|successful" (data pin = "sin[4]", clock pin = "clkin") is 6.528 ns
    Info: + Longest pin to register delay is 17.348 ns
        Info: 1: + IC(0.000 ns) + CELL(2.070 ns) = 2.070 ns; Loc. = PIN_20; Fanout = 5; PIN Node = 'sin[4]'
        Info: 2: + IC(9.173 ns) + CELL(1.278 ns) = 12.521 ns; Loc. = LC7_9_J2; Fanout = 1; COMB Node = 'qiangda:u1|Mux3~448'
        Info: 3: + IC(1.112 ns) + CELL(1.428 ns) = 15.061 ns; Loc. = LC9_9_J2; Fanout = 2; COMB Node = 'qiangda:u1|Mux3~449'
        Info: 4: + IC(0.304 ns) + CELL(1.428 ns) = 16.793 ns; Loc. = LC9_10_J2; Fanout = 1; COMB Node = 'qiangda:u1|successful~167'
        Info: 5: + IC(0.287 ns) + CELL(0.268 ns) = 17.348 ns; Loc. = LC10_10_J2; Fanout = 12; REG Node = 'qiangda:u1|successful'
        Info: Total cell delay = 6.472 ns ( 37.31 % )
        Info: Total interconnect delay = 10.876 ns ( 62.69 % )
    Info: + Micro setup delay of destination is 0.167 ns
    Info: - Shortest clock path from clock "clkin" to destination register is 10.987 ns
        Info: 1: + IC(0.000 ns) + CELL(2.070 ns) = 2.070 ns; Loc. = PIN_180; Fanout = 10; CLK Node = 'clkin'
        Info: 2: + IC(8.917 ns) + CELL(0.000 ns) = 10.987 ns; Loc. = LC10_10_J2; Fanout = 12; REG Node = 'qiangda:u1|successful'
        Info: Total cell delay = 2.070 ns ( 18.84 % )
        Info: Total interconnect delay = 8.917 ns ( 81.16 % )
Info: tco from clock "clkin" to destination pin "sh[3]" through register "daoji3:u3|CQI[3]" is 24.096 ns
    Info: + Longest clock path from clock "clkin" to source register is 14.925 ns
        Info: 1: + IC(0.000 ns) + CELL(2.070 ns) = 2.070 ns; Loc. = PIN_180; Fanout = 10; CLK Node = 'clkin'
        Info: 2: + IC(8.920 ns) + CELL(0.771 ns) = 11.761 ns; Loc. = LC7_10_J2; Fanout = 6; REG Node = 'daoji10:u2|CL'
        Info: 3: + IC(3.164 ns) + CELL(0.000 ns) = 14.925 ns; Loc. = LC3_11_J2; Fanout = 4; REG Node = 'daoji3:u3|CQI[3]'
        Info: Total cell delay = 2.841 ns ( 19.04 % )
        Info: Total interconnect delay = 12.084 ns ( 80.96 % )
    Info: + Micro clock to output delay of source is 0.512 ns
    Info: + Longest register to pin delay is 8.659 ns
        Info: 1: + IC(0.000 ns) + CELL(0.259 ns) = 0.259 ns; Loc. = LC3_11_J2; Fanout = 4; REG Node = 'daoji3:u3|CQI[3]'
        Info: 2: + IC(5.689 ns) + CELL(2.711 ns) = 8.659 ns; Loc. = PIN_53; Fanout = 0; PIN Node = 'sh[3]'
        Info: Total cell delay = 2.970 ns ( 34.30 % )
        Info: Total interconnect delay = 5.689 ns ( 65.70 % )
Info: th for register "daoji3:u3|CL" (data pin = "startin", clock pin = "clkin") is 2.704 ns
    Info: + Longest clock path from clock "clkin" to destination register is 14.931 ns
        Info: 1: + IC(0.000 ns) + CELL(2.070 ns) = 2.070 ns; Loc. = PIN_180; Fanout = 10; CLK Node = 'clkin'
        Info: 2: + IC(8.920 ns) + CELL(0.771 ns) = 11.761 ns; Loc. = LC7_10_J2; Fanout = 6; REG Node = 'daoji10:u2|CL'
        Info: 3: + IC(3.170 ns) + CELL(0.000 ns) = 14.931 ns; Loc. = LC3_10_J2; Fanout = 4; REG Node = 'daoji3:u3|CL'
        Info: Total cell delay = 2.841 ns ( 19.03 % )
        Info: Total interconnect delay = 12.090 ns ( 80.97 % )
    Info: + Micro hold delay of destination is 0.376 ns
    Info: - Shortest pin to register delay is 12.603 ns
        Info: 1: + IC(0.000 ns) + CELL(2.070 ns) = 2.070 ns; Loc. = PIN_11; Fanout = 17; PIN Node = 'startin'
        Info: 2: + IC(9.393 ns) + CELL(1.140 ns) = 12.603 ns; Loc. = LC3_10_J2; Fanout = 4; REG Node = 'daoji3:u3|CL'
        Info: Total cell delay = 3.210 ns ( 25.47 % )
        Info: Total interconnect delay = 9.393 ns ( 74.53 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Allocated 160 megabytes of memory during processing
    Info: Processing ended: Fri Apr 11 11:18:20 2008
    Info: Elapsed time: 00:00:03