📄 qiangdaqi.tan.rpt
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Classic Timing Analyzer report for qiangdaqi
Fri Apr 11 11:18:20 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
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; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clkin'
6. Clock Hold: 'clkin'
7. tsu
8. tco
9. th
10. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-----------------------+-----------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-----------------------+-----------------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 6.528 ns ; sin[4] ; qiangda:u1|successful ; -- ; clkin ; 0 ;
; Worst-case tco ; N/A ; None ; 24.096 ns ; daoji3:u3|CQI[3] ; sh[3] ; clkin ; -- ; 0 ;
; Worst-case th ; N/A ; None ; 2.704 ns ; startin ; daoji3:u3|CL ; -- ; clkin ; 0 ;
; Clock Setup: 'clkin' ; N/A ; None ; 144.32 MHz ( period = 6.929 ns ) ; daoji3:u3|CL ; qiangda:u1|data[0] ; clkin ; clkin ; 0 ;
; Clock Hold: 'clkin' ; Not operational: Clock Skew > Data Delay ; None ; N/A ; qiangda:u1|successful ; daoji3:u3|CL ; clkin ; clkin ; 5 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 5 ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-----------------------+-----------------------+------------+----------+--------------+
+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP20K300EQC240-3 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; Off ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clkin ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clkin' ;
+-------+------------------------------------------------+-----------------------+-----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-----------------------+-----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 144.32 MHz ( period = 6.929 ns ) ; daoji3:u3|CL ; qiangda:u1|data[0] ; clkin ; clkin ; None ; None ; 2.225 ns ;
; N/A ; 144.95 MHz ( period = 6.899 ns ) ; daoji3:u3|CL ; qiangda:u1|flag ; clkin ; clkin ; None ; None ; 2.253 ns ;
; N/A ; 145.05 MHz ( period = 6.894 ns ) ; daoji3:u3|CL ; qiangda:u1|data[1] ; clkin ; clkin ; None ; None ; 2.253 ns ;
; N/A ; 145.12 MHz ( period = 6.891 ns ) ; daoji3:u3|CL ; qiangda:u1|data[2] ; clkin ; clkin ; None ; None ; 2.253 ns ;
; N/A ; 145.79 MHz ( period = 6.859 ns ) ; daoji3:u3|CL ; qiangda:u1|successful ; clkin ; clkin ; None ; None ; 2.236 ns ;
; N/A ; 181.26 MHz ( period = 5.517 ns ) ; daoji10:u2|CQI[3] ; daoji10:u2|CL ; clkin ; clkin ; None ; None ; 5.047 ns ;
; N/A ; 185.63 MHz ( period = 5.387 ns ) ; daoji10:u2|CQI[2] ; daoji10:u2|CL ; clkin ; clkin ; None ; None ; 4.916 ns ;
; N/A ; 213.72 MHz ( period = 4.679 ns ) ; daoji10:u2|CQI[1] ; daoji10:u2|CL ; clkin ; clkin ; None ; None ; 4.212 ns ;
; N/A ; Restricted to 220.99 MHz ( period = 4.525 ns ) ; daoji10:u2|CQI[0] ; daoji10:u2|CL ; clkin ; clkin ; None ; None ; 3.490 ns ;
; N/A ; Restricted to 220.99 MHz ( period = 4.525 ns ) ; qiangda:u1|flag ; qiangda:u1|data[0] ; clkin ; clkin ; None ; None ; 3.070 ns ;
; N/A ; Restricted to 220.99 MHz ( period = 4.525 ns ) ; qiangda:u1|flag ; qiangda:u1|flag ; clkin ; clkin ; None ; None ; 3.098 ns ;
; N/A ; Restricted to 220.99 MHz ( period = 4.525 ns ) ; qiangda:u1|flag ; qiangda:u1|data[1] ; clkin ; clkin ; None ; None ; 3.098 ns ;
; N/A ; Restricted to 220.99 MHz ( period = 4.525 ns ) ; qiangda:u1|flag ; qiangda:u1|data[2] ; clkin ; clkin ; None ; None ; 3.098 ns ;
; N/A ; Restricted to 220.99 MHz ( period = 4.525 ns ) ; qiangda:u1|successful ; daoji10:u2|CL ; clkin ; clkin ; None ; None ; 3.065 ns ;
; N/A ; Restricted to 220.99 MHz ( period = 4.525 ns ) ; qiangda:u1|successful ; qiangda:u1|successful ; clkin ; clkin ; None ; None ; 3.058 ns ;
; N/A ; Restricted to 220.99 MHz ( period = 4.525 ns ) ; qiangda:u1|flag ; qiangda:u1|successful ; clkin ; clkin ; None ; None ; 2.950 ns ;
; N/A ; Restricted to 220.99 MHz ( period = 4.525 ns ) ; daoji10:u2|CL ; daoji10:u2|CL ; clkin ; clkin ; None ; None ; 2.902 ns ;
; N/A ; Restricted to 220.99 MHz ( period = 4.525 ns ) ; daoji3:u3|CQI[0] ; daoji3:u3|CL ; clkin ; clkin ; None ; None ; 2.590 ns ;
; N/A ; Restricted to 220.99 MHz ( period = 4.525 ns ) ; qiangda:u1|successful ; daoji10:u2|CQI[1] ; clkin ; clkin ; None ; None ; 2.374 ns ;
; N/A ; Restricted to 220.99 MHz ( period = 4.525 ns ) ; qiangda:u1|successful ; daoji10:u2|CQI[3] ; clkin ; clkin ; None ; None ; 2.377 ns ;
; N/A ; Restricted to 220.99 MHz ( period = 4.525 ns ) ; qiangda:u1|successful ; daoji10:u2|CQI[2] ; clkin ; clkin ; None ; None ; 2.378 ns ;
; N/A ; Restricted to 220.99 MHz ( period = 4.525 ns ) ; qiangda:u1|successful ; daoji10:u2|CQI[0] ; clkin ; clkin ; None ; None ; 2.358 ns ;
; N/A ; Restricted to 220.99 MHz ( period = 4.525 ns ) ; daoji3:u3|CQI[2] ; daoji3:u3|CL ; clkin ; clkin ; None ; None ; 2.523 ns ;
; N/A ; Restricted to 220.99 MHz ( period = 4.525 ns ) ; daoji3:u3|CQI[1] ; daoji3:u3|CL ; clkin ; clkin ; None ; None ; 2.423 ns ;
; N/A ; Restricted to 220.99 MHz ( period = 4.525 ns ) ; daoji10:u2|CQI[0] ; daoji10:u2|CQI[2] ; clkin ; clkin ; None ; None ; 2.419 ns ;
; N/A ; Restricted to 220.99 MHz ( period = 4.525 ns ) ; daoji10:u2|CQI[0] ; daoji10:u2|CQI[3] ; clkin ; clkin ; None ; None ; 2.416 ns ;
; N/A ; Restricted to 220.99 MHz ( period = 4.525 ns ) ; daoji10:u2|CQI[0] ; daoji10:u2|CQI[1] ; clkin ; clkin ; None ; None ; 2.409 ns ;
; N/A ; Restricted to 220.99 MHz ( period = 4.525 ns ) ; daoji3:u3|CQI[1] ; daoji3:u3|CQI[1] ; clkin ; clkin ; None ; None ; 1.723 ns ;
; N/A ; Restricted to 220.99 MHz ( period = 4.525 ns ) ; daoji3:u3|CQI[1] ; daoji3:u3|CQI[2] ; clkin ; clkin ; None ; None ; 1.723 ns ;
; N/A ; Restricted to 220.99 MHz ( period = 4.525 ns ) ; daoji3:u3|CQI[1] ; daoji3:u3|CQI[3] ; clkin ; clkin ; None ; None ; 1.723 ns ;
; N/A ; Restricted to 220.99 MHz ( period = 4.525 ns ) ; daoji10:u2|CQI[2] ; daoji10:u2|CQI[1] ; clkin ; clkin ; None ; None ; 1.709 ns ;
; N/A ; Restricted to 220.99 MHz ( period = 4.525 ns ) ; daoji10:u2|CQI[2] ; daoji10:u2|CQI[3] ; clkin ; clkin ; None ; None ; 1.709 ns ;
; N/A ; Restricted to 220.99 MHz ( period = 4.525 ns ) ; daoji10:u2|CQI[2] ; daoji10:u2|CQI[2] ; clkin ; clkin ; None ; None ; 1.709 ns ;
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