daoji3.vhd

来自「实现抢答器功能」· VHDL 代码 · 共 34 行

--倒时时为30秒
--首先是10位倒计时
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity daoji3 is
    Port ( EN,clk,rst :in std_logic;
           CQ : out std_logic_vector(3 downto 0);
           CL : out std_logic);
end daoji3;


architecture Behavioral of daoji3 is
signal CQI : std_logic_vector(3 downto 0);
begin
CQ<=CQI;
process(clk,rst)
begin
   if rst='0' then
		CQI<="0011";
   elsif CLK'EVENT AND CLK='1' then
         if EN='0' THEN
            if CQI > "0000" then
			   CQI<=CQI-1;CL <='0';
            else 
			  CQI<="0011";CL <='1';
           end if;
         end if;
  END IF;
  
  end process;
end Behavioral;