class.ptf

sopc builder 中网络的eth_ocm核

#
# This class.ptf file built by Component Editor
# 2008.02.19.16:45:25
#
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CLASS eth_ocm
{
   CB_GENERATOR 
   {
      HDL_FILES 
      {
         FILE 
         {
            use_in_simulation = "1";
            use_in_synthesis = "1";
            type = "verilog";
            filepath = "eth_ocm.v";
         }

      }
      top_module_name = "eth_ocm.v:eth_ocm";
      emit_system_h = "0";
   }
   MODULE_DEFAULTS global_signals
   {
      class = "eth_ocm";
      class_version = "7.2";
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Has_Clock = "1";
         Top_Level_Ports_Are_Enumerated = "1";
      }
      COMPONENT_BUILDER 
      {
         GLS_SETTINGS 
         {
         }
      }
      PORT_WIRING 
      {
         PORT av_clk
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "clk";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT av_reset
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "reset";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT mtx_clk_pad_i
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT mtxd_pad_o
         {
            width = "4";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT mtxen_pad_o
         {
            width = "1";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT mtxerr_pad_o
         {
            width = "1";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT mrx_clk_pad_i
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT mrxd_pad_i
         {
            width = "4";
            width_expression = "";
            direction = "input";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT mrxdv_pad_i
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT mrxerr_pad_i
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT mcoll_pad_i
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT mcrs_pad_i
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT mdc_pad_o
         {
            width = "1";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT md_pad_i
         {
            width = "1";
            width_expression = "";
            direction = "input";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT md_pad_o
         {
            width = "1";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
         PORT md_padoe_o
         {
            width = "1";
            width_expression = "";
            direction = "output";
            type = "export";
            is_shared = "0";
            vhdl_record_name = "";
            vhdl_record_type = "";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Is_Ethernet_Mac = "1";
         hdl_parameters 
         {
            total_descriptors = "128";
            tx_fifo_size_in_bytes = "128";
            rx_fifo_size_in_bytes = "4096";
         }
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL x101
            {
               name = "eth_ocm/global_signals";
               format = "Divider";
            }
            SIGNAL x102
            {
               name = "av_clk";
            }
            SIGNAL x103
            {
               name = "av_reset";
            }
            SIGNAL x104
            {
               name = "mtx_clk_pad_i";
            }
            SIGNAL x105
            {
               name = "mtxd_pad_o";
               radix = "hexadecimal";
            }
            SIGNAL x106
            {
               name = "mtxen_pad_o";
            }
            SIGNAL x107
            {
               name = "mtxerr_pad_o";
            }
            SIGNAL x108
            {
               name = "mrx_clk_pad_i";
            }
            SIGNAL x109
            {
               name = "mrxd_pad_i";
               radix = "hexadecimal";
            }
            SIGNAL x110
            {
               name = "mrxdv_pad_i";
            }
            SIGNAL x111
            {
               name = "mrxerr_pad_i";
            }
            SIGNAL x112
            {
               name = "mcoll_pad_i";
            }
            SIGNAL x113
            {
               name = "mcrs_pad_i";
            }
            SIGNAL x114
            {
               name = "mdc_pad_o";
            }
            SIGNAL x115
            {
               name = "md_pad_i";
            }
            SIGNAL x116
            {
               name = "md_pad_o";
            }
            SIGNAL x117
            {
               name = "md_padoe_o";
            }
            SIGNAL x118
            {
               name = "eth_ocm/control_port";
               format = "Divider";
            }
            SIGNAL x119
            {
               name = "av_address";
               radix = "hexadecimal";
            }
            SIGNAL x120
            {
               name = "av_read";
            }
            SIGNAL x121
            {
               name = "av_readdata";
               radix = "hexadecimal";
            }
            SIGNAL x122
            {
               name = "av_write";
            }
            SIGNAL x123
            {
               name = "av_writedata";
               radix = "hexadecimal";
            }
            SIGNAL x124
            {
               name = "av_chipselect";
            }
            SIGNAL x125
            {
               name = "av_waitrequest_n";
            }
            SIGNAL x126
            {
               name = "av_irq";
            }
            SIGNAL x127
            {
               name = "eth_ocm/rx_master";
               format = "Divider";
            }
            SIGNAL x128
            {
               name = "av_rx_address";
               radix = "hexadecimal";
            }
            SIGNAL x129
            {
               name = "av_rx_waitrequest";
            }
            SIGNAL x130
            {
               name = "av_rx_write";
            }
            SIGNAL x131
            {
               name = "av_rx_writedata";
               radix = "hexadecimal";
            }
            SIGNAL x132
            {
               name = "av_rx_byteenable";
               radix = "hexadecimal";
            }
            SIGNAL x133
            {
               name = "eth_ocm/tx_master";
               format = "Divider";
            }
            SIGNAL x134
            {
               name = "av_tx_address";
               radix = "hexadecimal";
            }
            SIGNAL x135
            {
               name = "av_tx_read";
            }
            SIGNAL x136
            {
               name = "av_tx_waitrequest";
            }
            SIGNAL x137
            {
               name = "av_tx_readdata";
               radix = "hexadecimal";
            }
            SIGNAL x138
            {
               name = "av_tx_readdatavalid";
            }
         }
      }
      SLAVE control_port
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Address_Group = "1";
            Has_Clock = "0";
            Address_Width = "10";
            Address_Alignment = "native";
            Data_Width = "32";
            Has_Base_Address = "1";
            Has_IRQ = "1";
            Setup_Time = "0";
            Hold_Time = "0";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Read_Latency = "0";
            Maximum_Pending_Read_Transactions = "0";
            Active_CS_Through_Read_Latency = "0";
            Is_Printable_Device = "0";
            Is_Memory_Device = "0";
            Is_Readable = "1";
            Is_Writable = "1";
            Minimum_Uninterrupted_Run_Length = "1";
         }
         COMPONENT_BUILDER 
         {
            AVS_SETTINGS 
            {
               Setup_Value = "0";
               Read_Wait_Value = "0";