eth_ocm.v

来自「sopc builder 中网络的eth_ocm核」· Verilog 代码 · 共 944 行 · 第 1/3 页

  .RxData(RxData),                      .RxValid(RxValid),                    .RxStartFrm(RxStartFrm), 
  .RxEndFrm(RxEndFrm),                  .ByteCnt(RxByteCnt), 
  .ByteCntEq0(RxByteCntEq0),            .ByteCntGreat2(RxByteCntGreat2),      .ByteCntMaxFrame(RxByteCntMaxFrame), 
  .CrcError(RxCrcError),                .StateIdle(RxStateIdle),              .StatePreamble(RxStatePreamble), 
  .StateSFD(RxStateSFD),                .StateData(RxStateData),
  .MAC(r_MAC),                          .r_Pro(r_Pro),                        .r_Bro(r_Bro),
  .r_HASH0(r_HASH0),                    .r_HASH1(r_HASH1),                    .RxAbort(RxAbort), 
  .AddressMiss(AddressMiss),            .PassAll(r_PassAll),                  .ControlFrmAddressOK(ControlFrmAddressOK)
);


// MII Carrier Sense Synchronization
always @ (posedge mtx_clk_pad_i or posedge av_reset)
begin
  if(av_reset)
    begin
      CarrierSense_Tx1 <= #Tp 1'b0;
      CarrierSense_Tx2 <= #Tp 1'b0;
    end
  else
    begin
      CarrierSense_Tx1 <= #Tp mcrs_pad_i;
      CarrierSense_Tx2 <= #Tp CarrierSense_Tx1;
    end
end

assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;


// MII Collision Synchronization
always @ (posedge mtx_clk_pad_i or posedge av_reset)
begin
  if(av_reset)
    begin
      Collision_Tx1 <= #Tp 1'b0;
      Collision_Tx2 <= #Tp 1'b0;
    end
  else
    begin
      Collision_Tx1 <= #Tp mcoll_pad_i;
      if(ResetCollision)
        Collision_Tx2 <= #Tp 1'b0;
      else
      if(Collision_Tx1)
        Collision_Tx2 <= #Tp 1'b1;
    end
end


// Synchronized Collision
assign Collision = ~r_FullD & Collision_Tx2;



// Delayed WillTransmit
always @ (posedge mrx_clk_pad_i)
begin
  WillTransmit_q <= #Tp WillTransmit;
  WillTransmit_q2 <= #Tp WillTransmit_q;
end 


assign Transmitting = ~r_FullD & WillTransmit_q2;



// Synchronized Receive Enable
always @ (posedge mrx_clk_pad_i or posedge av_reset)
begin
  if(av_reset)
    RxEnSync <= #Tp 1'b0;
  else
  if(~mrxdv_pad_i)
    RxEnSync <= #Tp r_RxEn;
end 



// Synchronizing WillSendControlFrame to WB_CLK;
always @ (posedge av_clk or posedge av_reset)
begin
  if(av_reset)
    WillSendControlFrame_sync1 <= 1'b0;
  else
    WillSendControlFrame_sync1 <=#Tp WillSendControlFrame;
end

always @ (posedge av_clk or posedge av_reset)
begin
  if(av_reset)
    WillSendControlFrame_sync2 <= 1'b0;
  else
    WillSendControlFrame_sync2 <=#Tp WillSendControlFrame_sync1;
end

always @ (posedge av_clk or posedge av_reset)
begin
  if(av_reset)
    WillSendControlFrame_sync3 <= 1'b0;
  else
    WillSendControlFrame_sync3 <=#Tp WillSendControlFrame_sync2;
end

always @ (posedge av_clk or posedge av_reset)
begin
  if(av_reset)
    RstTxPauseRq <= 1'b0;
  else
    RstTxPauseRq <=#Tp WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
end




// TX Pause request Synchronization
always @ (posedge mtx_clk_pad_i or posedge av_reset)
begin
  if(av_reset)
    begin
      TxPauseRq_sync1 <= #Tp 1'b0;
      TxPauseRq_sync2 <= #Tp 1'b0;
      TxPauseRq_sync3 <= #Tp 1'b0;
    end
  else
    begin
      TxPauseRq_sync1 <= #Tp (r_TxPauseRq & r_TxFlow);
      TxPauseRq_sync2 <= #Tp TxPauseRq_sync1;
      TxPauseRq_sync3 <= #Tp TxPauseRq_sync2;
    end
end


always @ (posedge mtx_clk_pad_i or posedge av_reset)
begin
  if(av_reset)
    TPauseRq <= #Tp 1'b0;
  else
    TPauseRq <= #Tp TxPauseRq_sync2 & (~TxPauseRq_sync3);
end


wire LatchedMRxErr;
reg RxAbort_latch;
reg RxAbort_sync1;
reg RxAbort_wb;
reg RxAbortRst_sync1;
reg RxAbortRst;

// Synchronizing RxAbort to the WISHBONE clock
always @ (posedge mrx_clk_pad_i or posedge av_reset)
begin
  if(av_reset)
    RxAbort_latch <= #Tp 1'b0;
  else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
    RxAbort_latch <= #Tp 1'b1;
  else if(RxAbortRst)
    RxAbort_latch <= #Tp 1'b0;
end

always @ (posedge av_clk or posedge av_reset)
begin
  if(av_reset)
    begin
      RxAbort_sync1 <= #Tp 1'b0;
      RxAbort_wb    <= #Tp 1'b0;
      RxAbort_wb    <= #Tp 1'b0;
    end
  else
    begin
      RxAbort_sync1 <= #Tp RxAbort_latch;
      RxAbort_wb    <= #Tp RxAbort_sync1;
    end
end

always @ (posedge mrx_clk_pad_i or posedge av_reset)
begin
  if(av_reset)
    begin
      RxAbortRst_sync1 <= #Tp 1'b0;
      RxAbortRst       <= #Tp 1'b0;
    end
  else
    begin
      RxAbortRst_sync1 <= #Tp RxAbort_wb;
      RxAbortRst       <= #Tp RxAbortRst_sync1;
    end
end



// Connecting Wishbone module
eth_avalon  #(  .DESC_COUNT     (TOTAL_DESCRIPTORS      ),
                .RX_FIFO_DEPTH  (RX_FIFO_SIZE_IN_BYTES  ),
                .TX_FIFO_DEPTH  (TX_FIFO_SIZE_IN_BYTES  ))  eth_avalon_inst
    (
    .av_reset                       (av_reset           ),
    .av_clk                         (av_clk             ),                    
    //Avalon Control port
      //inputs
    .av_cs                          (BDCs               ),
    .av_write                       (BDCs & av_write    ),
    .av_read                        (BDCs & av_read     ),
    .av_address                     (av_address[7:0]    ),
    .av_writedata                   (av_writedata       ), 
      //outputs
    .av_readdata                    (BD_av_readdata     ), 
    .av_waitrequest_n               (BDAck              ),

    //Avalon TX memory port
      //inputs
    .av_tx_waitrequest              (av_tx_waitrequest  ),
    .av_tx_readdatavalid            (av_tx_readdatavalid),
    .av_tx_readdata                 (av_tx_readdata     ),
      //outputs
    .av_tx_address                  (av_tx_address      ),
    .av_tx_read                     (av_tx_read         ),

    //Avalon RX memory port
      //inputs
    .av_rx_waitrequest              (av_rx_waitrequest  ),
      //outputs
    .av_rx_address                  (av_rx_address      ),
    .av_rx_write                    (av_rx_write        ),
    .av_rx_writedata                (av_rx_writedata    ),
    .av_rx_byteenable               (av_rx_byteenable   ),

    //TX
    .MTxClk                         (mtx_clk_pad_i),
    .TxStartFrm                     (TxStartFrm),
    .TxEndFrm                       (TxEndFrm), 
    .TxUsedData                     (TxUsedData),
    .TxData                         (TxData),
    .TxRetry                        (TxRetry),
    .TxAbort                        (TxAbort),
    .TxUnderRun                     (TxUnderRun), 
    .TxDone                         (TxDone), 
    .PerPacketCrcEn                 (PerPacketCrcEn),
    .PerPacketPad                   (PerPacketPad), 

    // Register
    .r_TxEn                         (r_TxEn),
    .r_RxEn                         (r_RxEn),
    .r_TxBDNum                      (r_TxBDNum), 
    .r_RxFlow                       (r_RxFlow),
    .r_PassAll                      (r_PassAll), 

    //RX
    .MRxClk                         (mrx_clk_pad_i),
    .RxData                         (RxData),
    .RxValid                        (RxValid), 
    .RxStartFrm                     (RxStartFrm),
    .RxEndFrm                       (RxEndFrm),                      
    .Busy_IRQ                       (Busy_IRQ),
    .RxE_IRQ                        (RxE_IRQ),
    .RxB_IRQ                        (RxB_IRQ), 
    .TxE_IRQ                        (TxE_IRQ),
    .TxB_IRQ                        (TxB_IRQ), 

    .RxAbort                        (RxAbort_wb),
    .RxStatusWriteLatched_sync2     (RxStatusWriteLatched_sync2), 

    .InvalidSymbol                  (InvalidSymbol),
    .LatchedCrcError                (LatchedCrcError),
    .RxLength                       (RxByteCnt),
    .RxLateCollision                (RxLateCollision),
    .ShortFrame                     (ShortFrame),
    .DribbleNibble                  (DribbleNibble),
    .ReceivedPacketTooBig           (ReceivedPacketTooBig),
    .LoadRxStatus                   (LoadRxStatus),
    .RetryCntLatched                (RetryCntLatched),
    .RetryLimit                     (RetryLimit),
    .LateCollLatched                (LateCollLatched),
    .DeferLatched                   (DeferLatched),   
    .RstDeferLatched                (RstDeferLatched), 
    .CarrierSenseLost               (CarrierSenseLost),
    .ReceivedPacketGood             (ReceivedPacketGood),
    .AddressMiss                    (AddressMiss),
    .ReceivedPauseFrm               (ReceivedPauseFrm)
  
`ifdef ETH_BIST
    ,
    .mbist_si_i                     (mbist_si_i),
    .mbist_so_o                     (mbist_so_o),
    .mbist_ctrl_i                   (mbist_ctrl_i)
`endif
);

// Connecting MacStatus module
eth_macstatus macstatus1 
(
  .MRxClk(mrx_clk_pad_i),             .Reset(av_reset),
  .ReceiveEnd(ReceiveEnd),            .ReceivedPacketGood(ReceivedPacketGood),     .ReceivedLengthOK(ReceivedLengthOK), 
  .RxCrcError(RxCrcError),            .MRxErr(MRxErr_Lb),                          .MRxDV(MRxDV_Lb), 
  .RxStateSFD(RxStateSFD),            .RxStateData(RxStateData),                   .RxStatePreamble(RxStatePreamble), 
  .RxStateIdle(RxStateIdle),          .Transmitting(Transmitting),                 .RxByteCnt(RxByteCnt), 
  .RxByteCntEq0(RxByteCntEq0),        .RxByteCntGreat2(RxByteCntGreat2),           .RxByteCntMaxFrame(RxByteCntMaxFrame), 
  .InvalidSymbol(InvalidSymbol),
  .MRxD(MRxD_Lb),                     .LatchedCrcError(LatchedCrcError),           .Collision(mcoll_pad_i),
  .CollValid(r_CollValid),            .RxLateCollision(RxLateCollision),           .r_RecSmall(r_RecSmall),
  .r_MinFL(r_MinFL),                  .r_MaxFL(r_MaxFL),                           .ShortFrame(ShortFrame),
  .DribbleNibble(DribbleNibble),      .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
  .LoadRxStatus(LoadRxStatus),        .RetryCnt(RetryCnt),                         .StartTxDone(StartTxDone),
  .StartTxAbort(StartTxAbort),        .RetryCntLatched(RetryCntLatched),           .MTxClk(mtx_clk_pad_i),
  .MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit),              .LateCollision(LateCollision),
  .LateCollLatched(LateCollLatched),  .DeferIndication(DeferIndication),           .DeferLatched(DeferLatched),
  .RstDeferLatched(RstDeferLatched), 
  .TxStartFrm(TxStartFrmOut),         .StatePreamble(StatePreamble),               .StateData(StateData),
  .CarrierSense(CarrierSense_Tx2),    .CarrierSenseLost(CarrierSenseLost),         .TxUsedData(TxUsedDataIn),
  .LatchedMRxErr(LatchedMRxErr),      .Loopback(r_LoopBck),                        .r_FullD(r_FullD)
);


endmodule