traffic.txt

本程序实现了一个十字路口的交通灯信号系统。在设计过程中借助硬件描述语言verilog hdl的强大行为级描述能力直接进行系统级描述。

module traffic(reset,clk,lampa,lampb,countera,counterb);
input reset;//复位信号
input clk;
output[3:0]  lampa;
output[3:0] lampb;
output[7:0] countera,counterb;
reg[3:0] lampa,lampb;
reg[7:0] countera,counteb;
parameter red_a =55,
     yellow_a = 5,
     green_a = 40,
     left_a  =15,
     left_b  =65
     yellow_b  =50,
     green_b   =30,
     left_b   =15;
parameter s1=8'b1000 0001, s2 = 8'b0100 0001, s3=8'b0010 0001, s4=8'b0100 001
               s5=8'b0001 1000,s6=8'b0001 0100,s7=8'b0001 0010,s8=8'b0001 0100;
      reg[5:0] s1_counter;
      reg[2:0] s2_counter;
      reg[3:0] s3_counter;
      reg[2:0] s4_counter;
      reg[4:0] s5_counter;
      reg[2:0] s6_counter;
      reg[3:0] s7_counter;
      reg[2:0] s8_counter;
      reg[7:0] state;
      always @(osedge reset or posedge clk)
        begin
          if (reset)
            begin
              counter_a <=40;
              counter_b <=65;
              lamp_a <=4'b1000;
              lamp_b <=4'b0001;
              s1_counter <40;
              s2_counter <=5;
              s3_counter <=15;
              s4_counter <=5;
              s5_counter <=30;
              s6_counter <=5;
              s7_counter <=15;
              s8_counter <=5;
              state <s1;
             end 
           else
              case(state)
                 s1: begin
                       counter_b <= counter_b - 1;
                       lamp_a <= 4'b1000;
                       lamp_b <= 4'b0001;
                       if (s1_counter > 0)
                         begin
                            s1_counter <= s1_counter - 1;
                            counter_a <= s1_counter;
                        end 
                      else
                        begin
                          state <= s2;
                          s1_counter <= green_a;
                          counter_a <= s2_counter;
                         end
                       end
                 s2: begin
                       counter_b <= counter_b - 1;
                       lamp_a <= 4'b0100;
                       lamp_b <= 4'b0001;
                       if (s2_counter > 0)
                         begin
                            s2_counter <= s2_counter - 1;
                            counter_a <= s2_counter;
                        end 
                      else
                        begin
                          state <= s3;
                          s2_counter <= yellow_a;
                          counter_a <= s3_counter;
                         end
                       end
                 s3: begin
                       counter_b <= counter_b - 1;
                       lamp_a <= 4'b0010;
                       lamp_b <= 4'b0001;
                       if (s3_counter > 0)
                         begin
                            s3_counter <= s3_counter - 1;
                            counter_a <= s3_counter;
                        end 
                      else
                        begin
                          state <= s4;
                          s3_counter <= left_a;
                          counter_a <= s4_counter;
                         end
                       end
                 s4: begin
                       counter_b <= counter_b - 1;
                       lamp_a <= 4'b0100;
                       lamp_b <= 4'b0001;
                       if (s4_counter > 0)
                         begin
                            s4_counter <= s4_counter - 1;
                            counter_a <= s4_counter;
                        end 
                      else
                        begin
                          state <= s5;
                          s4_counter <= yellow_a;
                          counter_a <= red_a;
                         end
                       end
                 s5: begin
                       counter_a <= counter_a - 1;
                       lamp_a <= 4'b0001;
                       lamp_b <= 4'b1000;
                       if (s5_counter > 0)
                         begin
                            s5_counter <= s5_counter - 1;
                            counter_b <= s5_counter;
                        end 
                      else
                        begin
                          state <= s6;
                          s5_counter <= green_b;
                          counter_b<= s6_counter;
                         end
                       end
                 s6: begin
                       counter_a <= counter_a - 1;
                       lamp_a <= 4'b0001;
                       lamp_b <= 4'b0100;
                       if (s6_counter > 0)
                         begin
                            s6_counter <= s6_counter - 1;
                            counter_b <= s6_counter;
                        end 
                      else
                        begin
                          state <= s7;
                          s6_counter <= yellow_b;
                          counter_b<= s7_counter;
                         end
                       end
                 s7: begin
                       counter_a <= counter_a - 1;
                       lamp_a <= 4'b0001;
                       lamp_b <= 4'b0010;
                       if (s7_counter > 0)
                         begin
                            s7_counter <= s7_counter - 1;
                            counter_b <= s7_counter;
                        end 
                      else
                        begin
                          state <= s8;
                          s7_counter <= left_b;
                          counter_b<= s8_counter;
                         end
                       end
                 s8: begin
                       counter_a <= counter_a - 1;
                       lamp_a <= 4'b0001;
                       lamp_b <= 4'b0100;
                       if (s8_counter > 0)
                         begin
                            s8_counter <= s8_counter - 1;
                            counter_b <= s8_counter;
                        end 
                        else
                        begin
                          state <= s1;
                          s8_counter <= yellow_b;
                          counter_b<= red_b;
                          end
                        end case
                       end
                   end module